图解M0的xPSR

 

• Application PSR (APSR)


The APSR contains the ALU flags: N (negative flag), Z (zero flag), C (carry or borrow flag),
and V (overflow flag). These bits are at the top 4 bits of the APSR. The common use of these
flags is to control conditional branches.

N (bit 31) Set to bit [31] of the result of the executed instruction. When it is “1”, the result has a negative
value (when interpreted as a signed integer). When it is “0”, the result has a positive value or
equal zero.
Z (bit 30) Set to “1” if the result of the executed instruction is zero. It can also be set to “1” after
a compare instruction is executed if the two values are the same.
C (bit 29) Carry flag of the result. For unsigned addition, this bit is set to “1” if an unsigned overflow
occurred. For unsigned subtract operations, this bit is the inverse of the borrow output
status.
V (bit 28) Overflow of the result. For signed addition or subtraction, this bit is set to “1” if a signed
overflow occurred.

In the Cortex-M0, almost all of the data processing instructions modify the APSR; however,
some of these instructions do not update the V flag or the C flag. For example, the MULS
(multiply) instruction only changes the N flag and the Z flag.

• Interrupt PSR (IPSR)

The IPSR contains the current executing interrupt service routine (ISR) number. Each
exception on the Cortex-M0 processor has a unique associated ISR number (exception type).
This is useful for identifying the current interrupt type during debugging and allows an
exception handler that is shared by several exceptions to know what exception it is serving.

 

• Execution PSR (EPSR)
The EPSR on the Cortex-M0 processor contains the T-bit, which indicates that the processor is
in the Thumb state. On the Cortex-M0 processor, this bit is normally set to 1 because the
Cortex-M0 only supports the Thumb state. If this bit is cleared, a hard fault exception will be
generated in the next instruction execution.

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