【UVM实战练习项目】4、UVM验证环境基本框架搭建（实例三）
实例三相对于实例二有以下变化：
- 在
packet_sequence中引入了变量，这些变量可被顶层配置，从而实现对发包数量的控制； - 增补了
reset_sequence，可调用factory用于覆盖，提高代码的可重用性； - 增补了
reset_agent，在reset_agent中将reset_sequencer例化，注意数据包参数变化reset_tr，生产新型数据，提高重用性； - 在
router_env中例化reset_agent，利用default_sequence启动reset_sequence； - 在测试用例中， 通过
uvm_config_db机制对item_count变量进行配置，设置发包数量；
文章目录
-
- 1.packet.sv（数据包）
- 2.packet_da_3.sv（添加约束包）
- 3.packet_sequence.sv（生产数据、声明配置变量）
- 4.reset_sequence.sv（可通过factory实现覆盖）
- 5.driver.sv（驱动数据）
- 6. input_agent.sv（代理）
- 7.reset_agent.sv（例化reset_sequencer，引入reset_sequence）
- 8.router_env.sv（环境，启动sequence生产数据）
- 9.test_collection.sv（测试用例，factory实现覆盖）
- 10.test.sv（主代码，启动UVM）
- 11.Makefile（make编译）
- 12.打印结果
1.packet.sv（数据包）
`ifndef PACKET_SV
`define PACKET_SV
class packet extends uvm_sequence_item;
rand bit[3:0] sa;
rand bit[3:0] da;
rand bit[7:0] payload[$]; //1.声明随机变量
`uvm_object_utils_begin(packet) //2.注册
`uvm_field_int(sa, UVM_ALL_ON|UVM_NOCOMPARE)
`uvm_field_int(da, UVM_ALL_ON)
`uvm_field_queue_int(payload, UVM_ALL_ON)
`uvm_object_utils_end
constraint valid{ //3.添加约束
payload.size inside {[1:10]};
}
function new(string name="packet"); //4.new()构造函数
super.new(name);
`uvm_info("TRACE",$sformatf("%m"),UVM_HIGH)
endfunction
endclass
`endif
2.packet_da_3.sv（添加约束包）
`ifndef PACKET_DA_3_SV
`define PACKET_DA_3_SV
class packet_da_3 extends packet;
`uvm_object_utils(packet_da_3)
constraint da_3{
da == 3;
}
function new(string name="packet_da_a"); //4.new()构造函数
super.new(name);
`uvm_info("TRACE",$sformatf("%m"),UVM_HIGH)
endfunction
endclass
`endif
3.packet_sequence.sv（生产数据、声明配置变量）
`ifndef PACKET_SEQUENCE_SV
`define PACKET_SEQUENCE_SV
`include "packet.sv" //0.将数据包引入sequence中
class packet_sequence extends uvm_sequence#(packet);
int item_count = 3; //在sequence中声明了新的配置变量
int port_id = 0;
bit [15:0] da_enable = 16'h1111;
int valid_da[$];
`uvm_object_utils_begin(packet_sequence) //1.注册
`uvm_field_int(item_count, UVM_ALL_ON)
`uvm_field_int(port_id, UVM_ALL_ON)
`uvm_field_int(da_enable, UVM_ALL_ON)
`uvm_field_queue_int(valid_da, UVM_ALL_ON)
`uvm_object_utils_end
function void pre_randomize(); //随机化之前配置变量
uvm_config_db#(int)::get(m_sequencer,"","item_count",item_count);
uvm_config_db#(int)::get(m_sequencer,"","port_id",port_id);
uvm_config_db#(bit[15:0])::get(m_sequencer,"","da_enable",da_enable);
if(!(port_id inside {-1, [0:15]}))begin
`uvm_fatal("CFGERR", $sformatf("Illegal port_id value of %0d", port_id))
end
valid_da.delete();
for(int i=0; i<16; i++)
if(da_enable[i])
valid_da.push_back(i);
endfunction
function new(string name="packet_sequence"); //2.new()构造函数
super.new(name);
`uvm_info("TRACE",$sformatf("%m"),UVM_HIGH)
endfunction
virtual task body(); //3.产生数据，对数据包随机化赋值
`uvm_info("TRACE",$sformatf("%m"),UVM_HIGH)
if(starting_phase != null)
starting_phase.raise_objection(this); //挂起objection
repeat(item_count)begin //配置发包数目，调用uvm_do宏
`uvm_do_with(req,{if(port_id == 1)
sa inside {[0:3]};
else
sa == port_id;
da inside valid_da;}
); //在参数化继承时，默认例化了包，例化名默认req
end
if(starting_phase != null)
starting_phase.drop_objection(this); //落下objection
endtask
endclass
`endif
4.reset_sequence.sv（可通过factory实现覆盖）
`ifndef RESET_SEQUENCE_SV
`define RESET_SEQUENCE_SV
class reset_tr extends uvm_sequence_item;
typedef enum{ASSERT, DEASSERT} kind_e;
rand kind_e kind;
rand int unsigned cycles = 1;
`uvm_object_utils_begin(reset_tr)
`uvm_field_enum(kind_e, kind, UVM_ALL_ON)
`uvm_field_int(cycles, UVM_ALL_ON)
`uvm_object_utils_end
function new(string name="reset_tr"); //2.new()构造函数
super.new(name);
`uvm_info("TRACE",$sformatf("%m"),UVM_HIGH)
endfunction
endclass
class reset_sequence extends uvm_sequence#(reset_tr);
`uvm_object_utils(reset_sequence)
function new(string name="reset_sequence"); //2.new()构造函数
super.new(name);
`uvm_info("TRACE",$sformatf("%m"),UVM_HIGH)
endfunction
virtual task body(); //3.产生数据，对数据包随机化赋值
`uvm_info("TRACE",$sformatf("%m"),UVM_HIGH)
if(starting_phase != null)
starting_phase.raise_objection(this); //挂起objection
repeat(10)begin //设置发包数目10，调用uvm_do宏
`uvm_info("RESET", "Executing Reset", UVM_MEDIUM)
end
if(starting_phase != null)
starting_phase.drop_objection(this); //落下objection
endtask
endclass
`endif
5.driver.sv（驱动数据）
`ifndef DRIVER_SV
`define DRIVER_SV
class driver extends uvm_driver#(packet);
`uvm_component_utils(driver) //1.注册
function new(string name,uvm_component parent); //2.new()构造函数
super.new(name,parent);
`uvm_info("TRACE",$sformatf("%m"),UVM_HIGH)
endfunction
virtual task run_phase(uvm_phase phase); //3.按照协议处理数据
`uvm_info("TRACE",$sformatf("%m"),UVM_HIGH)
forever begin
seq_item_port.get_next_item(req); //通过TLM端口申请数据
//req.print(); //数据按时序协议处理
`uvm_info("DRV_RUN", {"\n",req.sprint()}, UVM_MEDIUM)
seq_item_port.item_done(); //数据处理完毕，通知driver开始下一次数据传输
end
endtask
endclass
`endif
6. input_agent.sv（代理）
`ifndef INPUT_AGENT_SV
`define INPUT_AGENT_SV
`include "packet_sequence.sv"
`include "driver.sv" //引入packet_sequence.sv和driver.sv文件
typedef uvm_sequencer#(packet) packet_sequencer; //定义sequencer发送数据
class input_agent extends uvm_agent;
`uvm_component_utils(input_agent) //1.注册，声明子组件
packet_sequencer seqr;
driver drv;
function new(string name,uvm_component parent); //2.new()构造函数，确定父子关系
super.new(name,parent);
`uvm_info("TRACE",$sformatf("%m"),UVM_HIGH)
endfunction
virtual function void build_phase(uvm_phase phase); //3.在build_phase阶段实例化子组件
super.build_phase(phase);
`uvm_info("TRACE",$sformatf("%m"),UVM_HIGH)
seqr = packet_sequencer::type_id::create("seqr",this); //实例化子组件
drv = driver::type_id::create("drv",this); //实例化子组件
endfunction
virtual function void connect_phase(uvm_phase phase); //4.在connect_phase阶段建立seqr与drv之间的连接
super.connect_phase(phase);
`uvm_info("TRACE",$sformatf("%m"),UVM_HIGH)
drv.seq_item_port.connect(seqr.seq_item_export); //建立drv与seqr之间的连接
endfunction
endclass
`endif
7.reset_agent.sv（例化reset_sequencer，引入reset_sequence）
`ifndef RESET_AGENT_SV
`define RESET_AGENT_SV
`include "reset_sequence.sv" //引入reset_sequence.sv文件
typedef uvm_sequencer#(reset_tr) reset_sequencer; //定义sequencer发送数据
class reset_agent extends uvm_agent;
`uvm_component_utils(reset_agent) //1.注册，声明子组件
reset_sequencer seqr;
//driver drv;
function new(string name,uvm_component parent); //2.new()构造函数，确定父子关系
super.new(name,parent);
`uvm_info("TRACE",$sformatf("%m"),UVM_HIGH)
endfunction
virtual function void build_phase(uvm_phase phase); //3.在build_phase阶段实例化子组件
super.build_phase(phase);
`uvm_info("TRACE",$sformatf("%m"),UVM_HIGH)
seqr = reset_sequencer::type_id::create("seqr",this); //实例化子组件
//drv = driver::type_id::create("drv",this); //实例化子组件
endfunction
/* virtual function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
`uvm_info("TRACE",$sformatf("%m"),UVM_HIGH)
drv.seq_item_port.connect(seqr.seq_item_export);
endfunction */
endclass
`endif
8.router_env.sv（环境，启动sequence生产数据）
`ifndef ROUTER_ENV_SV
`define ROUTER_ENV_SV
`include "input_agent.sv" //将agent引入env中
`include "reset_agent.sv" //将新定义的reset_agent引入env中,并声明
class router_env extends uvm_env;
`uvm_component_utils(router_env) //1.注册
input_agent i_agent; //声明子组件
reset_agent r_agent;
function new(string name,uvm_component parent); //2.new()构造函数，确定父子关系
super.new(name,parent);
`uvm_info("TRACE",$sformatf("%m"),UVM_HIGH)
endfunction
virtual function void build_phase(uvm_phase phase); //3.在build_phase阶段实例化子组件
super.build_phase(phase);
`uvm_info("TRACE",$sformatf("%m"),UVM_HIGH)
i_agent = input_agent::type_id::create("i_agent",this); //实例化子组件
uvm_config_db#(uvm_object_wrapper)::set(this,"i_agent.seqr.main_phase","default_sequence",packet_sequence::get_type());
//采用default_sequence方式隐式启动seq，区别于（一）中的start()显式方式启动
r_agent = reset_agent::type_id::create("r_agent",this); //实例化子组件
uvm_config_db#(uvm_object_wrapper)::set(this,"r_agent.seqr.reset_phase","default_sequence",reset_sequence::get_type());
//采用default_sequence方式隐式启动seq，区别于（一）中的start()显式方式启动
endfunction
endclass
`endif
9.test_collection.sv（测试用例，factory实现覆盖）
`ifndef TEST_COLLECTION_SV
`define TEST_COLLECTION_SV
`include "router_env.sv" //将env引入test中
class test_base extends uvm_test; //基础用例
`uvm_component_utils(test_base) //1.注册
router_env env; //声明子组件
function new(string name,uvm_component parent); //2.new()构造函数，确定父子关系
super.new(name,parent);
`uvm_info("TRACE",$sformatf("%m"),UVM_HIGH)
endfunction
virtual function void build_phase(uvm_phase phase); //3. 实例化子组件
super.build_phase(phase);
`uvm_info("TRACE",$sformatf("%m"),UVM_HIGH)
env = router_env::type_id::create("env",this);
endfunction
virtual function void start_of_simulation_phase(uvm_phase phase); //4.打印拓扑结构
super.start_of_simulation_phase(phase);
`uvm_info("TRACE",$sformatf("%m"),UVM_HIGH)
uvm_top.print_topology(); //打印uvm的拓扑结构
factory.print(); //打印覆盖类型
endfunction
endclass
class test_da_3_seq extends test_base;
`uvm_component_utils(test_da_3_seq)
function new(string name,uvm_component parent); //2.new()构造函数，确定父子关系
super.new(name,parent);
`uvm_info("TRACE",$sformatf("%m"),UVM_HIGH)
endfunction
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
`uvm_info("TRACE",$sformatf("%m"),UVM_HIGH)
uvm_config_db#(bit[15:0])::set(this,"env.i_agent.seqr","da_enable",16'h000f);
uvm_config_db#(int)::set(this,"env.i_agent.seqr","item_count",20);
endfunction
endclass
`endif
10.test.sv（主代码，启动UVM）
program automatic test;
import uvm_pkg::*;
`include "uvm_macros.svh"
`include "test_collection.sv" //引入测试用例
initial begin
$timeformat(-9,1,"ns",10);
run_test();
end
endprogram
11.Makefile（make编译）
TB_TOP = ./test.sv
test = test_base
verbosity = UVM_MEDIUM
uvm_ver = uvm-1.1
seed = 1
defines = UVM_NO_DEPRECATED+UVM_OBJECT_MUST_HAVE_CONSTRUCTOR
SOLVER = 2
all: compile run
compile:
vcs -full64 -sverilog -ntb_opts ${uvm_ver} -timescale=1ns/1ns -l comp.log -debug_acc+all +vcs+vcdpluson ${TB_TOP} +define+${defines}
run:
./simv -l simv.log +ntb_random_seed=${seed} +UVM_TESTNAME=${test} +ntb_solver_mode=${SOLVER} +UVM_VERBOSITY=${verbosity}
clean:
rm -rf simv* csrc* *.tmp *.vpd *.key *.log *.h .vcs* DVE*
12.打印结果
make test=test_da_3_seq
完整log信息如下：
Command: /home/verifier/2023/router/blog/blog-4/./simv -l simv.log +ntb_random_seed=1 +UVM_TESTNAME=test_da_3_seq +ntb_solver_mode=2 +UVM_VERBOSITY=UVM_MEDIUM
Chronologic VCS simulator copyright 1991-2018
Contains Synopsys proprietary information.
Compiler version O-2018.09-SP2_Full64; Runtime version O-2018.09-SP2_Full64; Mar 28 03:42 2023
----------------------------------------------------------------
UVM-1.1d.Synopsys
(C) 2007-2013 Mentor Graphics Corporation
(C) 2007-2013 Cadence Design Systems, Inc.
(C) 2006-2013 Synopsys, Inc.
(C) 2011-2013 Cypress Semiconductor Corp.
----------------------------------------------------------------
VCD+ Writer O-2018.09-SP2_Full64 Copyright (c) 1991-2018 by Synopsys Inc.
UVM_INFO @ 0.0ns: reporter [RNTST] Running test test_da_3_seq...
UVM_INFO @ 0.0ns: reporter [UVMTOP] UVM testbench topology:
--------------------------------------------------------------
Name Type Size Value
--------------------------------------------------------------
uvm_test_top test_da_3_seq - @455
env router_env - @463
i_agent input_agent - @479
drv driver - @627
rsp_port uvm_analysis_port - @644
seq_item_port uvm_seq_item_pull_port - @635
seqr uvm_sequencer - @504
rsp_export uvm_analysis_export - @512
seq_item_export uvm_seq_item_pull_imp - @618
arbitration_queue array 0 -
lock_queue array 0 -
num_last_reqs integral 32 'd1
num_last_rsps integral 32 'd1
r_agent reset_agent - @491
seqr uvm_sequencer - @657
rsp_export uvm_analysis_export - @665
seq_item_export uvm_seq_item_pull_imp - @771
arbitration_queue array 0 -
lock_queue array 0 -
num_last_reqs integral 32 'd1
num_last_rsps integral 32 'd1
--------------------------------------------------------------
#### Factory Configuration (*)
No instance or type overrides are registered with this factory
All types registered with the factory: 49 total
(types without type names will not be printed)
Type Name
---------
driver
input_agent
packet
packet_sequence
reset_agent
reset_sequence
reset_tr
router_env
snps_uvm_reg_bank_group
snps_uvm_reg_map
test_base
test_da_3_seq
(*) Types with no associated type name will be printed as <unknown>
####
UVM_INFO reset_sequence.sv(34) @ 0.0ns: uvm_test_top.env.r_agent.seqr@@reset_sequence [RESET] Executing Reset
UVM_INFO reset_sequence.sv(34) @ 0.0ns: uvm_test_top.env.r_agent.seqr@@reset_sequence [RESET] Executing Reset
UVM_INFO reset_sequence.sv(34) @ 0.0ns: uvm_test_top.env.r_agent.seqr@@reset_sequence [RESET] Executing Reset
UVM_INFO reset_sequence.sv(34) @ 0.0ns: uvm_test_top.env.r_agent.seqr@@reset_sequence [RESET] Executing Reset
UVM_INFO reset_sequence.sv(34) @ 0.0ns: uvm_test_top.env.r_agent.seqr@@reset_sequence [RESET] Executing Reset
UVM_INFO reset_sequence.sv(34) @ 0.0ns: uvm_test_top.env.r_agent.seqr@@reset_sequence [RESET] Executing Reset
UVM_INFO reset_sequence.sv(34) @ 0.0ns: uvm_test_top.env.r_agent.seqr@@reset_sequence [RESET] Executing Reset
UVM_INFO reset_sequence.sv(34) @ 0.0ns: uvm_test_top.env.r_agent.seqr@@reset_sequence [RESET] Executing Reset
UVM_INFO reset_sequence.sv(34) @ 0.0ns: uvm_test_top.env.r_agent.seqr@@reset_sequence [RESET] Executing Reset
UVM_INFO reset_sequence.sv(34) @ 0.0ns: uvm_test_top.env.r_agent.seqr@@reset_sequence [RESET] Executing Reset
UVM_INFO driver.sv(17) @ 0.0ns: uvm_test_top.env.i_agent.drv [DRV_RUN]
------------------------------------------------------------------------------------------------
Name Type Size Value
------------------------------------------------------------------------------------------------
req packet - @830
sa integral 4 'h0
da integral 4 'h0
payload da(integral) 4 -
[0] integral 8 'h28
[1] integral 8 'haf
[2] integral 8 'hc3
[3] integral 8 'h2
begin_time time 64 0.0ns
depth int 32 'd2
parent sequence (name) string 15 packet_sequence
parent sequence (full name) string 45 uvm_test_top.env.i_agent.seqr.packet_sequence
sequencer string 29 uvm_test_top.env.i_agent.seqr
------------------------------------------------------------------------------------------------
UVM_INFO driver.sv(17) @ 0.0ns: uvm_test_top.env.i_agent.drv [DRV_RUN]
------------------------------------------------------------------------------------------------
Name Type Size Value
------------------------------------------------------------------------------------------------
req packet - @835
sa integral 4 'h0
da integral 4 'h1
payload da(integral) 8 -
[0] integral 8 'h7b
[1] integral 8 'h1f
[2] integral 8 'h3f
[3] integral 8 'hc5
[4] integral 8 'h75
[5] integral 8 'hff
[6] integral 8 'hb6
[7] integral 8 'hf9
begin_time time 64 0.0ns
depth int 32 'd2
parent sequence (name) string 15 packet_sequence
parent sequence (full name) string 45 uvm_test_top.env.i_agent.seqr.packet_sequence
sequencer string 29 uvm_test_top.env.i_agent.seqr
------------------------------------------------------------------------------------------------
UVM_INFO driver.sv(17) @ 0.0ns: uvm_test_top.env.i_agent.drv [DRV_RUN]
------------------------------------------------------------------------------------------------
Name Type Size Value
------------------------------------------------------------------------------------------------
req packet - @839
sa integral 4 'h0
da integral 4 'h3
payload da(integral) 3 -
[0] integral 8 'hf2
[1] integral 8 'h67
[2] integral 8 'hb
begin_time time 64 0.0ns
depth int 32 'd2
parent sequence (name) string 15 packet_sequence
parent sequence (full name) string 45 uvm_test_top.env.i_agent.seqr.packet_sequence
sequencer string 29 uvm_test_top.env.i_agent.seqr
------------------------------------------------------------------------------------------------
UVM_INFO driver.sv(17) @ 0.0ns: uvm_test_top.env.i_agent.drv [DRV_RUN]
------------------------------------------------------------------------------------------------
Name Type Size Value
------------------------------------------------------------------------------------------------
req packet - @843
sa integral 4 'h0
da integral 4 'h0
payload da(integral) 8 -
[0] integral 8 'h1d
[1] integral 8 'he4
[2] integral 8 'h77
[3] integral 8 'hab
[4] integral 8 'hf5
[5] integral 8 'h73
[6] integral 8 'h64
[7] integral 8 'h48
begin_time time 64 0.0ns
depth int 32 'd2
parent sequence (name) string 15 packet_sequence
parent sequence (full name) string 45 uvm_test_top.env.i_agent.seqr.packet_sequence
sequencer string 29 uvm_test_top.env.i_agent.seqr
------------------------------------------------------------------------------------------------
UVM_INFO driver.sv(17) @ 0.0ns: uvm_test_top.env.i_agent.drv [DRV_RUN]
------------------------------------------------------------------------------------------------
Name Type Size Value
------------------------------------------------------------------------------------------------
req packet - @847
sa integral 4 'h0
da integral 4 'h3
payload da(integral) 2 -
[0] integral 8 'h2c
[1] integral 8 'hc8
begin_time time 64 0.0ns
depth int 32 'd2
parent sequence (name) string 15 packet_sequence
parent sequence (full name) string 45 uvm_test_top.env.i_agent.seqr.packet_sequence
sequencer string 29 uvm_test_top.env.i_agent.seqr
------------------------------------------------------------------------------------------------
UVM_INFO driver.sv(17) @ 0.0ns: uvm_test_top.env.i_agent.drv [DRV_RUN]
------------------------------------------------------------------------------------------------
Name Type Size Value
------------------------------------------------------------------------------------------------
req packet - @851
sa integral 4 'h0
da integral 4 'h1
payload da(integral) 4 -
[0] integral 8 'h1b
[1] integral 8 'h8f
[2] integral 8 'h4b
[3] integral 8 'h84
begin_time time 64 0.0ns
depth int 32 'd2
parent sequence (name) string 15 packet_sequence
parent sequence (full name) string 45 uvm_test_top.env.i_agent.seqr.packet_sequence
sequencer string 29 uvm_test_top.env.i_agent.seqr
------------------------------------------------------------------------------------------------
UVM_INFO driver.sv(17) @ 0.0ns: uvm_test_top.env.i_agent.drv [DRV_RUN]
------------------------------------------------------------------------------------------------
Name Type Size Value
------------------------------------------------------------------------------------------------
req packet - @855
sa integral 4 'h0
da integral 4 'h0
payload da(integral) 1 -
[0] integral 8 'had
begin_time time 64 0.0ns
depth int 32 'd2
parent sequence (name) string 15 packet_sequence
parent sequence (full name) string 45 uvm_test_top.env.i_agent.seqr.packet_sequence
sequencer string 29 uvm_test_top.env.i_agent.seqr
------------------------------------------------------------------------------------------------
UVM_INFO driver.sv(17) @ 0.0ns: uvm_test_top.env.i_agent.drv [DRV_RUN]
------------------------------------------------------------------------------------------------
Name Type Size Value
------------------------------------------------------------------------------------------------
req packet - @859
sa integral 4 'h0
da integral 4 'h1
payload da(integral) 4 -
[0] integral 8 'hb2
[1] integral 8 'hd2
[2] integral 8 'h2a
[3] integral 8 'hc5
begin_time time 64 0.0ns
depth int 32 'd2
parent sequence (name) string 15 packet_sequence
parent sequence (full name) string 45 uvm_test_top.env.i_agent.seqr.packet_sequence
sequencer string 29 uvm_test_top.env.i_agent.seqr
------------------------------------------------------------------------------------------------
UVM_INFO driver.sv(17) @ 0.0ns: uvm_test_top.env.i_agent.drv [DRV_RUN]
------------------------------------------------------------------------------------------------
Name Type Size Value
------------------------------------------------------------------------------------------------
req packet - @863
sa integral 4 'h0
da integral 4 'h2
payload da(integral) 9 -
[0] integral 8 'hb9
[1] integral 8 'h27
[2] integral 8 'hbc
[3] integral 8 'h87
[4] integral 8 'ha
[5] integral 8 'h22
[6] integral 8 'h36
[7] integral 8 'h81
[8] integral 8 'heb
begin_time time 64 0.0ns
depth int 32 'd2
parent sequence (name) string 15 packet_sequence
parent sequence (full name) string 45 uvm_test_top.env.i_agent.seqr.packet_sequence
sequencer string 29 uvm_test_top.env.i_agent.seqr
------------------------------------------------------------------------------------------------
UVM_INFO driver.sv(17) @ 0.0ns: uvm_test_top.env.i_agent.drv [DRV_RUN]
------------------------------------------------------------------------------------------------
Name Type Size Value
------------------------------------------------------------------------------------------------
req packet - @867
sa integral 4 'h0
da integral 4 'h3
payload da(integral) 2 -
[0] integral 8 'h29
[1] integral 8 'hc9
begin_time time 64 0.0ns
depth int 32 'd2
parent sequence (name) string 15 packet_sequence
parent sequence (full name) string 45 uvm_test_top.env.i_agent.seqr.packet_sequence
sequencer string 29 uvm_test_top.env.i_agent.seqr
------------------------------------------------------------------------------------------------
UVM_INFO driver.sv(17) @ 0.0ns: uvm_test_top.env.i_agent.drv [DRV_RUN]
------------------------------------------------------------------------------------------------
Name Type Size Value
------------------------------------------------------------------------------------------------
req packet - @871
sa integral 4 'h0
da integral 4 'h0
payload da(integral) 5 -
[0] integral 8 'hac
[1] integral 8 'hf5
[2] integral 8 'hb5
[3] integral 8 'h1e
[4] integral 8 'hf1
begin_time time 64 0.0ns
depth int 32 'd2
parent sequence (name) string 15 packet_sequence
parent sequence (full name) string 45 uvm_test_top.env.i_agent.seqr.packet_sequence
sequencer string 29 uvm_test_top.env.i_agent.seqr
------------------------------------------------------------------------------------------------
UVM_INFO driver.sv(17) @ 0.0ns: uvm_test_top.env.i_agent.drv [DRV_RUN]
------------------------------------------------------------------------------------------------
Name Type Size Value
------------------------------------------------------------------------------------------------
req packet - @875
sa integral 4 'h0
da integral 4 'h1
payload da(integral) 9 -
[0] integral 8 'hf9
[1] integral 8 'h98
[2] integral 8 'h5a
[3] integral 8 'h13
[4] integral 8 'h23
[5] integral 8 'h72
[6] integral 8 'h6f
[7] integral 8 'h2b
[8] integral 8 'hd7
begin_time time 64 0.0ns
depth int 32 'd2
parent sequence (name) string 15 packet_sequence
parent sequence (full name) string 45 uvm_test_top.env.i_agent.seqr.packet_sequence
sequencer string 29 uvm_test_top.env.i_agent.seqr
------------------------------------------------------------------------------------------------
UVM_INFO driver.sv(17) @ 0.0ns: uvm_test_top.env.i_agent.drv [DRV_RUN]
------------------------------------------------------------------------------------------------
Name Type Size Value
------------------------------------------------------------------------------------------------
req packet - @879
sa integral 4 'h0
da integral 4 'h3
payload da(integral) 3 -
[0] integral 8 'h24
[1] integral 8 'h36
[2] integral 8 'hf8
begin_time time 64 0.0ns
depth int 32 'd2
parent sequence (name) string 15 packet_sequence
parent sequence (full name) string 45 uvm_test_top.env.i_agent.seqr.packet_sequence
sequencer string 29 uvm_test_top.env.i_agent.seqr
------------------------------------------------------------------------------------------------
UVM_INFO driver.sv(17) @ 0.0ns: uvm_test_top.env.i_agent.drv [DRV_RUN]
------------------------------------------------------------------------------------------------
Name Type Size Value
------------------------------------------------------------------------------------------------
req packet - @883
sa integral 4 'h0
da integral 4 'h0
payload da(integral) 2 -
[0] integral 8 'h6f
[1] integral 8 'hf
begin_time time 64 0.0ns
depth int 32 'd2
parent sequence (name) string 15 packet_sequence
parent sequence (full name) string 45 uvm_test_top.env.i_agent.seqr.packet_sequence
sequencer string 29 uvm_test_top.env.i_agent.seqr
------------------------------------------------------------------------------------------------
UVM_INFO driver.sv(17) @ 0.0ns: uvm_test_top.env.i_agent.drv [DRV_RUN]
------------------------------------------------------------------------------------------------
Name Type Size Value
------------------------------------------------------------------------------------------------
req packet - @887
sa integral 4 'h0
da integral 4 'h0
payload da(integral) 3 -
[0] integral 8 'h91
[1] integral 8 'hd
[2] integral 8 'h7d
begin_time time 64 0.0ns
depth int 32 'd2
parent sequence (name) string 15 packet_sequence
parent sequence (full name) string 45 uvm_test_top.env.i_agent.seqr.packet_sequence
sequencer string 29 uvm_test_top.env.i_agent.seqr
------------------------------------------------------------------------------------------------
UVM_INFO driver.sv(17) @ 0.0ns: uvm_test_top.env.i_agent.drv [DRV_RUN]
------------------------------------------------------------------------------------------------
Name Type Size Value
------------------------------------------------------------------------------------------------
req packet - @891
sa integral 4 'h0
da integral 4 'h0
payload da(integral) 2 -
[0] integral 8 'h80
[1] integral 8 'h68
begin_time time 64 0.0ns
depth int 32 'd2
parent sequence (name) string 15 packet_sequence
parent sequence (full name) string 45 uvm_test_top.env.i_agent.seqr.packet_sequence
sequencer string 29 uvm_test_top.env.i_agent.seqr
------------------------------------------------------------------------------------------------
UVM_INFO driver.sv(17) @ 0.0ns: uvm_test_top.env.i_agent.drv [DRV_RUN]
------------------------------------------------------------------------------------------------
Name Type Size Value
------------------------------------------------------------------------------------------------
req packet - @895
sa integral 4 'h0
da integral 4 'h3
payload da(integral) 3 -
[0] integral 8 'h4e
[1] integral 8 'hb
[2] integral 8 'hb
begin_time time 64 0.0ns
depth int 32 'd2
parent sequence (name) string 15 packet_sequence
parent sequence (full name) string 45 uvm_test_top.env.i_agent.seqr.packet_sequence
sequencer string 29 uvm_test_top.env.i_agent.seqr
------------------------------------------------------------------------------------------------
UVM_INFO driver.sv(17) @ 0.0ns: uvm_test_top.env.i_agent.drv [DRV_RUN]
------------------------------------------------------------------------------------------------
Name Type Size Value
------------------------------------------------------------------------------------------------
req packet - @899
sa integral 4 'h0
da integral 4 'h1
payload da(integral) 10 -
[0] integral 8 'ha0
[1] integral 8 'h94
[2] integral 8 'hce
[3] integral 8 'h41
[4] integral 8 'h1
[5] integral 8 'h9
[6] integral 8 'hb2
[7] integral 8 'h69
[8] integral 8 'hc8
[9] integral 8 'h46
begin_time time 64 0.0ns
depth int 32 'd2
parent sequence (name) string 15 packet_sequence
parent sequence (full name) string 45 uvm_test_top.env.i_agent.seqr.packet_sequence
sequencer string 29 uvm_test_top.env.i_agent.seqr
------------------------------------------------------------------------------------------------
UVM_INFO driver.sv(17) @ 0.0ns: uvm_test_top.env.i_agent.drv [DRV_RUN]
------------------------------------------------------------------------------------------------
Name Type Size Value
------------------------------------------------------------------------------------------------
req packet - @903
sa integral 4 'h0
da integral 4 'h0
payload da(integral) 6 -
[0] integral 8 'h8e
[1] integral 8 'hca
[2] integral 8 'h98
[3] integral 8 'h9
[4] integral 8 'ha9
[5] integral 8 'hec
begin_time time 64 0.0ns
depth int 32 'd2
parent sequence (name) string 15 packet_sequence
parent sequence (full name) string 45 uvm_test_top.env.i_agent.seqr.packet_sequence
sequencer string 29 uvm_test_top.env.i_agent.seqr
------------------------------------------------------------------------------------------------
UVM_INFO driver.sv(17) @ 0.0ns: uvm_test_top.env.i_agent.drv [DRV_RUN]
------------------------------------------------------------------------------------------------
Name Type Size Value
------------------------------------------------------------------------------------------------
req packet - @907
sa integral 4 'h0
da integral 4 'h3
payload da(integral) 1 -
[0] integral 8 'h54
begin_time time 64 0.0ns
depth int 32 'd2
parent sequence (name) string 15 packet_sequence
parent sequence (full name) string 45 uvm_test_top.env.i_agent.seqr.packet_sequence
sequencer string 29 uvm_test_top.env.i_agent.seqr
------------------------------------------------------------------------------------------------
--- UVM Report Summary ---
** Report counts by severity
UVM_INFO : 32
UVM_WARNING : 0
UVM_ERROR : 0
UVM_FATAL : 0
** Report counts by id
[DRV_RUN] 20
[RESET] 10
[RNTST] 1
[UVMTOP] 1
$finish called from file "/opt/synopsys/vcs/vcs-mx/O-2018.09-SP2/etc/uvm-1.1/base/uvm_root.svh", line 439.
$finish at simulation time 0.0ns
V C S S i m u l a t i o n R e p o r t
Time: 0 ns
CPU Time: 0.320 seconds; Data structure size: 0.5Mb
Tue Mar 28 03:42:34 2023