xtensa 汇编

xtensa-modules.c

The ESP8266

Zephyr API Documentation: zephyr/arch/xtensa/irq.h Source File

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https://mirrors.spacecruft.org/zephyrproject-rtos/zephyr/commit/31706c874e08a8da463782726317351bfdf646c6

soc: xtensa: Add SoC definition for Audio DSP on Intel Apollolake · 31706c874e - zephyr - SpaceCruft! Mirrorssoc: xtensa: Add SoC definition for Audio DSP on Intel Apollolake · 31706c874e - zephyr - SpaceCruft! Mirrors[0738] 在TIE描述中的第2个步骤是定义一个新的指令类，它含有新指令SAD。这就是SAD 指令的各操作数被定义的地方。在这种情况下，SAD包括3个寄存器操作数，目标寄存器arr， 源寄存器ars和art。如前面所指出的那样，arr被定义为用该指令的字段r索引的寄存器， ars和art被定义为用该指令的字段s和t索引的寄存器。

https://patents.google.com/patent/CN1382280B/zh

Uses Of Instruction Fields
op0 Major opcode
op1 4-bit sub-opcode for 24-bit instructions
op2 4-bit sub-opcode for 24-bit instructions
r
AR target (result), BR target (result),
4-bit immediate,
4-bit sub-opcode
s
AR source, BR source,
AR target
t
AR target, BR target,
AR source, BR source,
4-bit sub-opcode
zephyr/reset-vector.S at main · intel/zephyr · GitHubzephyr/reset-vector.S at main · intel/zephyr · GitHub