【FPGA】数码管扫描

目录

实验原理 

源代码

管脚配置

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实验芯片：xc7a100tlc sg324-2L

实验原理 

 

 

 

 

源代码

        顶层模块

`timescale 1ns / 1ps

module LED_Tube(
    input clk_100M,
    input rst_, //reset控制扫描模块和计数模块清零
    input start, //start不控制扫描模块，
    output[7:0] AN,
    output[7:0] seg
);
wire clk_ref; //数码管刷新频率：500hz
wire clk_inc; //数字刷新频率：10hz
wire[31:0] data; 
 
Fdiv fdiv1(clk_100M,32'd100000,clk_ref);
Fdiv fdiv2(clk_100M,32'd5000000,clk_inc);
Counter counter(clk_inc,rst_,start,data);
Scanner scanner(data,rst_,clk_ref,AN,seg);
endmodule

       

        分频器模块

`timescale 1ns / 1ps

module Fdiv(
    input clk_in,
    input[31:0] f,
    output reg clk_out
);
reg[31:0] cnt;

always@(posedge clk_in)
begin
    if(cnt == f)
        begin
            clk_out <= ~clk_out;
            cnt <= 1'b0;
        end
    else
        cnt <= cnt + 1'b1; 
end
endmodule

       

        计数模块

`timescale 1ns / 1ps

module Counter(
    input clk_inc,
    input rst_,
    input start,
    output reg[31:0] data
);

always@(negedge rst_ or posedge clk_inc)
begin
    if(!rst_)
        data <= 1'b0;
    else if(start)
    begin
        if(data[3:0] == 4'b1001) begin
            data[3:0] <= 4'b0000;
            if(data[7:4] == 4'b1001) begin
                data[7:4] <= 4'b0000;
                if(data[11:8] == 4'b1001) begin
                    data[11:8] <= 4'b0000;
                    if(data[15:12] == 4'b1001) begin
                        data[15:12] <= 4'b0000;
                        if(data[19:16] == 4'b1001) begin
                            data[19:16] <= 4'b0000;
                            if(data[23:20] == 4'b1001) begin
                                data[23:20] <= 4'b0000;
                                if(data[27:24] == 4'b1001) begin
                                    data[27:24] <= 4'b0000;
                                    if(data[31:28] == 4'b1001)
                                        data[31:28] <= 4'b0000;
                                    else
                                        data[31:28] <= data[31:28] + 1'b1;
                                end
                                else
                                    data[27:24] <= data[27:24] + 1'b1;
                            end
                            else
                                data[23:20] <= data[23:20] + 1'b1;
                        end
                        else
                            data[19:16] <= data[19:16] + 1'b1;
                    end
                    else
                        data[15:12] <= data[15:12] + 1'b1;
                end
                else
                    data[11:8] <= data[11:8] + 1'b1;
            end
            else
                data[7:4] <= data[7:4] + 1'b1;
        end
        else
            data[3:0] <= data[3:0] + 1'b1;
    end
end
endmodule

       

        扫描数码管模块

`timescale 1ns / 1ps

module Scanner(
    input[31:0] data,
    input rst_,
    input clk_ref,
    output reg[7:0] AN,
    output reg[7:0] seg
    );
reg[3:0] data_x;
reg[2:0] bit_sel;

always@(negedge rst_ or posedge clk_ref)
begin
    if(!rst_)
        bit_sel <= 3'd0;
    else
        bit_sel <= bit_sel + 1'b1;
end

always@(*)
    begin
        case(bit_sel)
            3'b000: begin AN <= 8'b1111_1110; data_x <= data[3:0]; end
            3'b001: begin AN <= 8'b1111_1101; data_x <= data[7:4]; end
            3'b010: begin AN <= 8'b1111_1011; data_x <= data[11:8]; end
            3'b011: begin AN <= 8'b1111_0111; data_x <= data[15:12]; end
            3'b100: begin AN <= 8'b1110_1111; data_x <= data[19:16]; end
            3'b101: begin AN <= 8'b1101_1111; data_x <= data[23:20]; end
            3'b110: begin AN <= 8'b1011_1111; data_x <= data[27:24]; end
            3'b111: begin AN <= 8'b0111_1111; data_x <= data[31:28]; end
         endcase
         
         case(data_x)
            4'b0000: seg <= 8'b0000_0011;
            4'b0001: seg <= 8'b1001_1111;
            4'b0010: seg <= 8'b0010_0101;
            4'b0011: seg <= 8'b0000_1101;
            
            4'b0100: seg <= 8'b1001_1001;
            4'b0101: seg <= 8'b0100_1001;
            4'b0110: seg <= 8'b0100_0001;
            4'b0111: seg <= 8'b0001_1111;
            
            4'b1000: seg <= 8'b0000_0001;
            4'b1001: seg <= 8'b0000_1001;
        endcase
     end
endmodule

管脚配置

set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN E3} [get_ports clk_100M]

set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN V5} [get_ports rst_]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN T4} [get_ports start]

set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN C9} [get_ports AN[7]]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN C10} [get_ports AN[6]]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN D10} [get_ports AN[5]]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN C11} [get_ports AN[4]]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN M17} [get_ports AN[3]]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN J14} [get_ports AN[2]]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN K13} [get_ports AN[1]]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN P14} [get_ports AN[0]]

set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN F14} [get_ports seg[7]]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN N14} [get_ports seg[6]]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN J13} [get_ports seg[5]]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN G13} [get_ports seg[4]]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN F13} [get_ports seg[3]]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN G14} [get_ports seg[2]]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN M13} [get_ports seg[1]]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN H14} [get_ports seg[0]]