Modelsim完成4位二进制异步复位计数器

仅供参考

1.代码截图

2.测试代码截图

 

 

3.波形截图 

4.程序代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity jsq is
  port(clk,rst:in std_logic;
        co:out std_logic;
        cnt:out std_logic_vector(0 to 3));
end jsq;
architecture jgt of jsq is
  begin
    process(clk,rst)
      variable cnt_n:std_logic_vector(0 to 3):="0000";
      begin
        if(rst='1') then
        cnt_n:="0000";
        co<='0';
        cnt<="0000";
        elsif(clk'event and clk='1')then
          cnt_n:=cnt_n+"0001";
              co<='0';
          if cnt_n="1111" then
              cnt_n:="0000";
              co<='1';
            end if;
          end if;
            cnt<=cnt_n;
          end process;
        end jgt;

5.测试代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity jsq_t is
  end entity jsq_t;
architecture jgt_t of jsq_t is
  component jsq is
      port(clk,rst:in std_logic;
        co:out std_logic;
        cnt:out std_logic_vector(0 to 3));
    end component jsq;
    signal clk,rst:std_logic:='0';
    signal co:std_logic:='0';
    signal cnt:std_logic_vector(0 to 3);
  begin
    instant:jsq port map
      (
      clk=>clk,co=>co,cnt=>cnt,rst=>rst
    );
    process
      begin
      rst<='0';
      wait for 50 ns;
      rst<='1';
      wait for 50 ns;
      rst<='0';
      wait;
    end process;
    process
      begin
        clk<='0';
        wait for 20 ns;
        clk<='1';
        wait for 20 ns;
        clk<='0';
        wait for 20 ns;
        clk<='1';
        wait for 20 ns;
        end process;
end architecture jgt_t;