1.Shift4
module top_module(
input clk,
input areset, // async active-high reset to zero
input load,
input ena,
input [3:0] data,
output reg [3:0] q);
always@(posedge clk or posedge areset) begin
if(areset)
q<=0;
else
if(load)
q<=data;
else
if(ena)
q={1'b0,q[3],q[2],q[1]};
else
q<=q;
end
endmodule
2.Rotate100
module top_module(
input clk,
input load,
input [1:0] ena,
input [99:0] data,
output reg [99:0] q);
always@(posedge clk) begin
if(load)
q<=data;
else
if(ena==2'b01)
q<={q[0],q[99:1]};
else
if(ena==2'b10)
q<={q[98:0],q[99]};
else
q<=q;
end
endmodule
3.Shift18
module top_module(
input clk,
input load,
input ena,
input [1:0] amount,
input [63:0] data,
output reg [63:0] q
);
always @(posedge clk) begin
if (load) begin
q <= data;
end
else if (ena) begin
case(amount)
2'b00 : q <= {q[62:0],1'b0};
2'b01 : q <= {q[55:0],8'b0};
2'b10 : q <= {q[63],q[63:1]};
2'b11 : q <= {{8{q[63]}},q[63:8]};
endcase
end
end
endmodule
4.Lfsr5
module top_module(
input clk,
input reset, // Active-high synchronous reset to 5'h1
output [4:0] q
);
always @(posedge clk) begin
if (reset) begin
q <= 5'h1;
end
else begin
q[4] <= q[0];
q[3] <= q[4];
q[2] <= q[3] ^ q[0];
q[1] <= q[2];
q[0] <= q[1];
end
end
endmodule
5.mt2015_lfsr
module top_module (
input [2:0] SW, // R
input [1:0] KEY, // L and clk
output [2:0] LEDR); // Q
wire q0 ,q1,q2;
wire r0,r1,r2;
wire L,clk;
assign {L,clk}=KEY;
assign {r2,r1,r0}=SW;
assign LEDR={q2,q1,q0};
zuhe U1(q2,r0,L,clk,q0);
zuhe U2(q0,r1,L,clk,q1);
zuhe U3(q2^q1,r2,L,clk,q2);
endmodule
module zuhe(a,b,c,clk,q);
input a,b,c,clk;
output q;
always@(posedge clk) begin
q<=c?b:a;
end
endmodule
6.Lfsr32
module top_module(
input clk,
input reset, // Active-high synchronous reset to 32'h1
output [31:0] q
);
always @(posedge clk) begin
if (reset) begin
q <= 32'h1;
end
else begin
q[31] <= q[0];
q[30] <= q[31];
q[29] <= q[30];
q[28] <= q[29];
q[27] <= q[28];
q[26] <= q[27];
q[25] <= q[26];
q[24] <= q[25];
q[23] <= q[24];
q[22] <= q[23];
q[21] <= q[22] ^ q[0];
q[20] <= q[21];
q[19] <= q[20];
q[18] <= q[19];
q[17] <= q[18];
q[16] <= q[17];
q[15] <= q[16];
q[14] <= q[15];
q[13] <= q[14];
q[12] <= q[13];
q[11] <= q[12];
q[10] <= q[11];
q[9] <= q[10];
q[8] <= q[9];
q[7] <= q[8];
q[6] <= q[7];
q[5] <= q[6];
q[4] <= q[5];
q[3] <= q[4];
q[2] <= q[3];
q[1] <= q[2] ^ q[0];
q[0] <= q[1] ^ q[0];
end
end
endmodule
7.exams/m2014_q4k
module top_module (
input clk,
input resetn, // synchronous reset
input in,
output out);
reg q1,q2,q3;
always@(posedge clk) begin
if(!resetn)begin
q1<=0;
q2<=0;
q3<=0;
out<=0;
end
else begin
q1<=in;
q2<=q1;
q3<=q2;
out<=q3;
end
end
endmodule
8.exams/2014_q4b
module top_module (
input [3:0] SW,
input [3:0] KEY,
output [3:0] LEDR
); //
wire clk,E,L,W;
wire[3:0] R;
reg[3:0] Q;
assign {W,L,E,clk}=KEY;
assign R=SW;
assign LEDR=Q;
reg[3:0] a,b;
MUXDFF U1(W,E,R[3],L,clk,Q[3]);
MUXDFF U2(Q[3],E,R[2],L,clk,Q[2]);
MUXDFF U3(Q[2],E,R[1],L,clk,Q[1]);
MUXDFF U4(Q[1],E,R[0],L,clk,Q[0]);
endmodule
module MUXDFF (w,e,r,l,clk,Q);
input w,e,r,l,clk;
output Q;
reg a,b;
assign a=e?w:Q;
assign b=l?r:a;
always@(posedge clk) begin
Q<=b;
end
endmodule
9.exams/ece241_2013_q12
module top_module (
input clk,
input enable,
input S,
input A, B, C,
output Z );
reg [7:0] Q;
always@(posedge clk) begin
if(enable)
Q={Q[6:0],S};
else
Q<=Q;
end
assign Z=Q[{A,B,C}];
endmodule
