1.Sim/circuit1
module top_module (
input a,
input b,
output q );//
assign q = a&b; // Fix me
endmodule
2.Sim/circuit2
module top_module (
input a,
input b,
input c,
input d,
output q );//
assign q = ~(a^b^c^d); // Fix me
endmodule
3.Sim/circuit3
module top_module (
input a,
input b,
input c,
input d,
output q );//
assign q = b&d | a&d | b&c | a&c ;// Fix me
endmodule
4.Sim/circuit4
module top_module (
input a,
input b,
input c,
input d,
output q );//
assign q = b||c; // Fix me
endmodule
5.Sim/circuit5
module top_module (
input [3:0] a,
input [3:0] b,
input [3:0] c,
input [3:0] d,
input [3:0] e,
output [3:0] q
);
always @(*) begin
case(c)
0: begin
q = b;
end
1: begin
q = e;
end
2: begin
q = a;
end
3: begin
q = d;
end
default:begin
q = 'd15;
end
endcase
end
endmodule
6.Sim/circuit6
module top_module (
input [2:0] a,
output [15:0] q
);
always @(*) begin
case(a)
0: q = 16'h1232;
1: q = 16'haee0;
2: q = 16'h27d4;
3: q = 16'h5a0e;
4: q = 16'h2066;
5: q = 16'h64ce;
6: q = 16'hc526;
7: q = 16'h2f19;
endcase
end
endmodule
7.Sim/circuit7
module top_module (
input clk,
input a,
output q
);
always @(posedge clk) begin
q <= ~a;
end
endmodule
8.Sim/circuit8
module top_module (
input clock,
input a,
output p,
output q );
always@(*) begin
if(clock)
p<=a;
end
always@(negedge clock) begin
q<=p;
end
endmodule
9.Sim/circuit9
module top_module (
input clk,
input a,
output [3:0] q );
always@(posedge clk ) begin
if(a==1)
q<=4;
else if(q==6)
q<=0;
else
q<=q+1;
end
endmodule
10.Sim/circuit10
module top_module (
input clk,
input a,
input b,
output q,
output state
);
assign q = a^b^state;
always @(posedge clk) begin
if (a&b) begin
state <= 'd1;
end
else if (~a&~b) begin
state <= 'd0;
end
else begin
state <= state;
end
end
endmodule
