HDLbits---Verification writing Testbenches

1.Tb/clock

module top_module ( );
       reg clk;
    initial begin
        clk = 1'b0;
    end
    always #5 clk = ~clk;
    dut u1 (.clk(clk));

endmodule

2.Tb/tb1

module top_module ( output reg A, output reg B );//

    // generate input patterns here
    initial begin

   
        A = 'd0;
        B = 'd0;
        #10
        A = 'd1;
        #5
        B = 'd1;
        #5
        A = 'd0;
        #20
        B = 'd0;
   

    end

endmodule

3.Tb/and

module top_module();
    reg in_0,in_1;
    reg out;
    initial begin
        in_0 = 1'b0;
        in_1 = 1'b0;
        #10
        in_0 = 1'b1;
        #10
        in_0 = 1'b0;
        in_1 = 1'b1;
        #10
        in_0 = 1'b1;
    end
    andgate u1 (.in({in_1,in_0}),.out(out));
endmodule

4.Tb/tb2

module top_module();
    reg clk,in;
    reg [2:0] s;
    reg out;
   always #5 clk = ~clk; 
    
    initial begin
        clk=0;
        in = 1'b0;
        s = 3'b010;
        
        #10
        s = 3'b110;
        #10
        in = 1'b1;
        s = 3'b010;
        #10
        in = 1'b0;
        s = 3'b111;
        #10
        in = 1'b1;
        s = 3'b000;
        #30 in = 1'b0;
    end
    
    q7 u1 (.clk(clk),.in(in),.s(s),.out(out));
endmodule

5.Tb/tff

module top_module ();
    reg clk,reset,t;
    wire q;
    initial begin
        clk = 0;
        reset = 0;
        t = 0;
        #5 reset =1;
        #10 reset = 0;
    end
    always #5 clk = ~clk;
    always @(posedge clk)
        begin
            if(reset)
                t <= 1;
            else
                t <= 0;
        end   
    tff u1 (.clk(clk),.reset(reset),.t(t),.q(q));
endmodule