VerilogHDL学习教程-HDLBits网站

VerilogHDL学习教程-HDLBits网站

在学习VerilogHDL语言的过程中，作为初学者小白不免有疑惑要从哪里开始。在这里我推荐夏宇闻老师的《Verilog数字系统设计教程》和HDLBits网站。在学习的过程中将前者作为一本工具书，只需要认真仔细的看一遍，做好重点标注。在学习过程中可以HDLBits网站为主要练习的手段，但是在HDLBits网站进行学习和练习时候不能闭门造车，自己完成训练后还是要看看网上其他人的写法，了解一下有没有可以借鉴的地方。HDL网站一共有180道题，在这里我会按照网站的划分分期书写，并在其中写下我自己搜集的资料和自己的感悟。

HDLBits_Getting Started

• Getting Started
• Output Zero

HDLBits_Verilog Language

Basics

• Simple
• wire
• Four wires
• Inverter
• AND gate
• NOR gate
• XNOR gate
• Declaring
• wires
• 7458 chip

Vectors

• Vectors
• Vectors in more detail
• Vector part select
• Bitwise operators
• Four-input gates
• Vector concatenation operator
• Vector reversal 1
• Replication operator
• More replication

Modules: Hierarchy

Modules
Connecting ports by position
Connecting ports by name
Three modules
Modules and vectors
Adder 1
Adder 2
Carry-select adder
Adder-subtractor
Procedures
Procedures include always, initial, task, and function blocks. Procedures allow sequential statements (which cannot be used outside of a procedure) to be used to describe the behaviour of a circuit.

Always blocks (combinational)
Always blocks (clocked)
If statement
If statement latches
Case statement
Priority encoder
Priority encoder with casez
Avoiding latches
More Verilog Features
Conditional ternary operator
Reduction operators
Reduction: Even wider gates
Combinational for-loop: Vector reversal 2
Combinational for-loop: 255-bit population count
Generate for-loop: 100-bit binary adder 2
Generate for-loop: 100-digit BCD adder

Circuits

Combinational Logic
Basic Gates

文章还在慢慢整理与更新

参考资料来源
[1]:知乎-HDLBits 中文导学