Exams/m2014 q4k

Implement the following circuit:

 

module top_module (
    input clk,
    input resetn,   // synchronous reset
    input in,
    output out);

    reg[2:0] temp;
    always @ (posedge clk)
        if(resetn == 0) begin
            out <= 1'b0;
        temp <= 3'b0;
        end    
    else
        begin
            temp[0] <= in;
            temp[1] <= temp[0];
            temp[2] <= temp[1];
            out <= temp[2];
        end
endmodule