(Verilog) wire和reg，以及always

For combinational always blocks, always use a sensitivity list of (*). Explicitly listing out the signals is error-prone (if you miss one), and is ignored for hardware synthesis. If you explicitly specify the sensitivity list and miss a signal, the synthesized hardware will still behave as though (*) was specified, but the simulation will not and not match the hardware's behaviour. (In SystemVerilog, use always_comb.)

A note on wire vs. reg: The left-hand-side of an assign statement must be a net type (e.g., wire), while the left-hand-side of a procedural assignment (in an always block) must be a variable type (e.g., reg). These types (wire vs. reg) have nothing to do with what hardware is synthesized, and is just syntax left over from Verilog's use as a hardware simulation language.

对于组合always块，总是使用(*）的敏感性列表。明确列出信号是容易出错的（如果你漏掉一个），并且在硬件合成中会被忽略。如果你明确指定了敏感性列表但漏掉了一个信号，合成后的硬件将仍然按照(*)指定的方式工作，但仿真将不会与硬件的行为相匹配。（在SystemVerilog中，请使用always_comb）。

关于wire和reg的注意事项：assign语句的左边必须是一个网络类型（如wire），而过程赋值（在always块中）的左边必须是一个变量类型（如reg）。这些类型（wire vs. reg）与合成的硬件无关，只是Verilog作为硬件仿真语言的语法剩下的部分。