quartus modelsim仿真时钟出现Pu1是什么意思？

FPGA实验，用rom的IP核做一个简易信号发生器。仿真出来没有波形，时钟信号显示Pu1，复位信号显示HiZ。
有大佬知道原因的麻烦指导一下，仿真界面，工程文件如下：
modelsim输出

顶层文件sin_gen.v

module sin_gen (clk,rst,q_outs);

   input clk,rst;
	output [7:0] q_outs;
	//output [7:0] q_outt;
	//output [7:0] q_outw;	

	reg [8:0] addr;
	
always @(posedge clk or negedge rst)

begin
   if(!rst)
	    addr <= 10'd0;
	else if(addr == 10'd511)
	    addr <= 10'd0;
	else
       addr <= addr + 1'b1;
end 
rom	rom_inst (
	.address ( addr ),
	.clock ( clk ),
	.q ( q_outs )
	);
endmodule

测试文件sin_gen.vt

// Copyright (C) 2018  Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License 
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors.  Please
// refer to the applicable agreement for further details.

// *****************************************************************************
// This file contains a Verilog test bench template that is freely editable to  
// suit user's needs .Comments are provided in each section to help the user    
// fill out necessary details.                                                  
// *****************************************************************************
// Generated on "04/30/2023 16:59:30"
                                                                                
// Verilog Test Bench template for design : sin_gen
// 
// Simulation tool : ModelSim (Verilog)
// 

`timescale 1 ns/ 1 ns
module sin_gen_vlg_tst();
// constants                                           
// general purpose registers
reg eachvec;
// test vector input registers
reg clk;
reg rst;
// wires                                               
wire [7:0]  q_outs;
//wire [7:0]  q_outt;
//wire [7:0]  q_outw;

initial
begin
   clk = 0;
	rst = 0;
	# 15
	rst = 1;
end
// assign statements (if any)                          
sin_gen i1 (
// port map - connection between master ports and signals/registers   
	.clk(clk),
	.rst(rst),
	.q_outs(q_outs)
	//.q_outt(q_outt),
	//.q_outw(q_outw),	
);
always #10 clk =~clk;                                                  
endmodule

江湖救急，感谢！感谢！