Xilinx AXI VIP使用教程

Xilinx提供了用于验证AXI相关设计的AXI VIP(AXI Verification IP),它可以对自己设计的AXI接口模块进行全方位的验证(如使用VIP的Master、Passthrough、Slave三种模式对自己写的AXI接口进行仿真验证),提前规避和发现一些不满足AXI总线规范的设计问题。本文以Master AXI VIP为例,介绍其使用方法。

1. 创建block design

Xilinx AXI VIP使用教程_第1张图片
此处默认block design的名字为design_1

2. 添加相关ip

  1. 输入axi vip,添加axi vip ip核

Xilinx AXI VIP使用教程_第2张图片
Xilinx AXI VIP使用教程_第3张图片
2. INTERFACE MODE选择MASTER
3. 添加AXI BRAM Controller和Block Memory Generator IP。同时将AXI BRAM Controller的接口数减少为1个。
Xilinx AXI VIP使用教程_第4张图片
Xilinx AXI VIP使用教程_第5张图片
4. 按下图所示进行连线
Xilinx AXI VIP使用教程_第6张图片
5. 为时钟和复位信号创建输入端口。
Xilinx AXI VIP使用教程_第7张图片
6. 分配地址空间, Validate Design, Generate Output Products, 然后Create HDL Wrapper.
在这里插入图片描述

  1. 创建testbench,语言类型选择system verilog。代码如下:
`timescale 1ns / 1ps

import axi_vip_pkg::*;
import design_1_axi_vip_0_0_pkg::*;

module tb_top();

bit clk;
bit aresetn;

//used in API and parital randomization for transaction generation and data read back from driver
axi_transaction                         wr_transaction;                // Write transaction
axi_transaction                         rd_transaction;                // Read transaction

xil_axi_uint                            mtestWID;                      // Write ID  
xil_axi_ulong                           mtestWADDR;                    // Write ADDR  
xil_axi_len_t                           mtestWBurstLength;             // Write Burst Length   
xil_axi_size_t                          mtestWDataSize;                // Write SIZE  
xil_axi_burst_t                         mtestWBurstType;               // Write Burst Type  
xil_axi_uint                            mtestRID;                      // Read ID  
xil_axi_ulong                           mtestRADDR;                    // Read ADDR  
xil_axi_len_t                           mtestRBurstLength;             // Read Burst Length   
xil_axi_size_t                          mtestRDataSize;                // Read SIZE  
xil_axi_burst_t                         mtestRBurstType;               // Read Burst Type  
xil_axi_lock_t                          mtestLOCK;                     // LOCK value for WRITE/READ_BURST transaction
xil_axi_cache_t                         mtestCacheType = 3;            // Cache Type value for WRITE/READ_BURST transaction
xil_axi_prot_t                          mtestProtectionType = 3'b000;  // Protection Type value for WRITE/READ_BURST transaction
xil_axi_region_t                        mtestRegion = 4'b000;          // Region value for WRITE/READ_BURST transaction
xil_axi_qos_t                           mtestQOS = 4'b000;             // QOS value for WRITE/READ_BURST transaction
xil_axi_data_beat                       dbeat;                         // Data beat value for WRITE/READ_BURST transaction
xil_axi_user_beat                       usrbeat;                       // User beat value for WRITE/READ_BURST transaction
xil_axi_data_beat [255:0]               mtestWUSER;                    // Wuser value for WRITE/READ_BURST transaction
xil_axi_data_beat                       mtestAWUSER = 'h0;             // Awuser value for WRITE/READ_BURST transaction
xil_axi_data_beat                       mtestARUSER = 0;               // Aruser value for WRITE/READ_BURST transaction
xil_axi_data_beat [255:0]               mtestRUSER;                    // Ruser value for WRITE/READ_BURST transaction
xil_axi_uint                            mtestBUSER = 0;                // Buser value for WRITE/READ_BURST transaction
xil_axi_resp_t                          mtestBresp;                    // Bresp value for WRITE/READ_BURST transaction
xil_axi_resp_t[255:0]                   mtestRresp;                    // Rresp value for WRITE/READ_BURST transaction

bit [63:0]                             mtestWData;                     // Write Data
bit[8*4096-1:0]                        Wdatablock;                     // Write data block
xil_axi_data_beat                      Wdatabeat[];                    // Write data beats

bit [63:0]                             mtestRData;                     // Read Data
bit[8*4096-1:0]                        Rdatablock;                     // Read data block
xil_axi_data_beat                      Rdatabeat[];                    // Read data beats


  initial begin
    aresetn = 1'b0;
    clk = 1'b0;
    #100ns;
    aresetn = 1'b1;
  end
   
  always #10 clk <= ~clk;

design_1 u_dut(
    .aclk       (clk     ),
    .aresetn    (aresetn )
);

design_1_axi_vip_0_0_mst_t              mst_agent;

initial begin
    mst_agent = new("master vip agent",u_dut.axi_vip_0.inst.IF);
    mst_agent.start_master();               // mst_agent start to run
    mtestWID = $urandom_range(0,(1<<(0)-1)); 
    mtestWADDR = 'hc000_1000;//$urandom_range(0,(1<<(32)-1));
    mtestWBurstLength = 0;
    mtestWDataSize = xil_axi_size_t'(xil_clog2((32)/8));
    mtestWBurstType = XIL_AXI_BURST_TYPE_INCR;
    mtestWData = 'h12345678;//$urandom();
    $display("mtestWDataSize = %d", mtestWDataSize);
    //single write transaction filled in user inputs through API 
    single_write_transaction_api("single write with api",
                                 .id(mtestWID),
                                 .addr(mtestWADDR),
                                 .len(mtestWBurstLength), 
                                 .size(mtestWDataSize),
                                 .burst(mtestWBurstType),
                                 .wuser(mtestWUSER),
                                 .awuser(mtestAWUSER), 
                                 .data(mtestWData)
                                 );
                                  
    mtestRID = $urandom_range(0,(1<<(0)-1));
    mtestRADDR = mtestWADDR;
    mtestRBurstLength = 0;
    mtestRDataSize = xil_axi_size_t'(xil_clog2((32)/8)); 
    mtestRBurstType = XIL_AXI_BURST_TYPE_INCR;
    
    $display("mtestRDataSize = %d", mtestRDataSize);
    //single read transaction filled in user inputs through API 
    single_read_transaction_api("single read with api",
                                 .id(mtestRID),
                                 .addr(mtestRADDR),
                                 .len(mtestRBurstLength), 
                                 .size(mtestRDataSize),
                                 .burst(mtestRBurstType)
                                 );
end

  task automatic single_write_transaction_api ( 
                                input string                     name ="single_write",
                                input xil_axi_uint               id =0, 
                                input xil_axi_ulong              addr =0,
                                input xil_axi_len_t              len =0, 
                                input xil_axi_size_t             size =xil_axi_size_t'(xil_clog2((32)/8)),
                                input xil_axi_burst_t            burst =XIL_AXI_BURST_TYPE_INCR,
                                input xil_axi_lock_t             lock = XIL_AXI_ALOCK_NOLOCK,
                                input xil_axi_cache_t            cache =3,
                                input xil_axi_prot_t             prot =0,
                                input xil_axi_region_t           region =0,
                                input xil_axi_qos_t              qos =0,
                                input xil_axi_data_beat [255:0]  wuser =0, 
                                input xil_axi_data_beat          awuser =0,
                                input bit [63:0]              data =0
                                                );
    axi_transaction                               wr_trans;
    $display("single_write_transaction_api size = %d", size);
    wr_trans = mst_agent.wr_driver.create_transaction(name);
    wr_trans.set_write_cmd(addr,burst,id,len,size);
    wr_trans.set_prot(prot);
    wr_trans.set_lock(lock);
    wr_trans.set_cache(cache);
    wr_trans.set_region(region);
    wr_trans.set_qos(qos);
    wr_trans.set_data_block(data);
    mst_agent.wr_driver.send(wr_trans);   
  endtask  : single_write_transaction_api 
 
  task automatic single_read_transaction_api ( 
                                    input string                     name ="single_read",
                                    input xil_axi_uint               id =0, 
                                    input xil_axi_ulong              addr =0,
                                    input xil_axi_len_t              len =0, 
                                    input xil_axi_size_t             size =xil_axi_size_t'(xil_clog2((32)/8)),
                                    input xil_axi_burst_t            burst =XIL_AXI_BURST_TYPE_INCR,
                                    input xil_axi_lock_t             lock =XIL_AXI_ALOCK_NOLOCK ,
                                    input xil_axi_cache_t            cache =3,
                                    input xil_axi_prot_t             prot =0,
                                    input xil_axi_region_t           region =0,
                                    input xil_axi_qos_t              qos =0,
                                    input xil_axi_data_beat          aruser =0
                                                );
    axi_transaction                               rd_trans;
    $display("single_read_transaction_api size = %d", size);
    rd_trans = mst_agent.rd_driver.create_transaction(name);
    rd_trans.set_read_cmd(addr,burst,id,len,size);
    rd_trans.set_prot(prot);
    rd_trans.set_lock(lock);
    rd_trans.set_cache(cache);
    rd_trans.set_region(region);
    rd_trans.set_qos(qos);
    mst_agent.rd_driver.send(rd_trans);   
  endtask  : single_read_transaction_api

endmodule

其中,import design_1_axi_vip_0_0_pkg::*;design_1_axi_vip_0_0_mst_t mst_agent;语句中的design_1为block_design名称。需根据实际情况修改。

design_1 u_dut(
    .aclk       (clk     ),
    .aresetn    (aresetn )
);

是对顶层设计模块的例化,模块名以及接口信号名称也需要根据实际情况修改,使之对应。
8. 运行仿真,并观察波形。
Xilinx AXI VIP使用教程_第8张图片

你可能感兴趣的:(fpga开发)