HDLBits—Exams/ece241 2014 q7b

依然是错题整理

From a 1000 Hz clock, derive a 1 Hz signal, called OneHertz, that could be used to drive an Enable signal for a set of hour/minute/second counters to create a digital wall clock. Since we want the clock to count once per second, the OneHertz signal must be asserted for exactly one cycle each second. Build the frequency divider using modulo-10 (BCD) counters and as few other gates as possible. Also output the enable signals from each of the BCD counters you use (c_enable[0] for the fastest counter, c_enable[2] for the slowest).

The following BCD counter is provided for you. Enable must be high for the counter to run. Reset is synchronous and set high to force the counter to zero. All counters in your circuit must directly use the same 1000 Hz signal.

module bcdcount (
	input clk,
	input reset,
	input enable,
	output reg [3:0] Q
);

上面是网站提供的原题干

读题错误理解为：1000Hz产生一个1Hz（OneHertz），然后这个这个信号激活一次，时钟秒分时动一次，然后给了BCD十位计数器，针对秒分59进位一次，而时针的进位未知（不清楚24小时制还是12小时制），只能先边写边看，0~999（三个十进制计数），秒分时（六个），最痛苦的是怎么改都不对（题都没读懂怎么可能对）

瞥见左边目录 大师我悟了.jpg：不用管秒分时，直接三个计数器构成0~999，即为count1000，计数999时产生一个OneHert就可以了

module top_module (
    input clk,
    input reset,
    output OneHertz,
    output [2:0] c_enable
); //
    wire reset0,reset1,reset2;
    wire[3:0] c0,c1,c2;
    assign c_enable[0] = 1;
    assign c_enable[1] = (c0==9)?(1):(0);
    assign c_enable[2] = (c0==9&c1==9)?(1):(0);
    assign reset0 = (c0==9)?(1):(reset);
    assign reset1 = (c1==9&c0==9)?(1):(reset);
    assign reset2 = (c2==9&c1==9&c0==9)?(1):(reset);
    assign OneHertz = (c2==9&c1==9&c0==9)?(1):(0);
    bcdcount counter0 (clk, reset0, c_enable[0], c0/*, ... */);
    bcdcount counter1 (clk, reset1, c_enable[1], c1/*, ... */);
    bcdcount counter2 (clk, reset2, c_enable[2], c2/*, ... */);
endmodule