HDLbits--Exams/ece241 2014 q7b

module top_module (
    input clk,
    input reset,
    output OneHertz,
    output [2:0] c_enable
); //
    
    reg[3:0] q1,q2,q3;
    
    assign c_enable[0] ='b1;
    assign c_enable[1] = q1&&!(q1%9);
    assign c_enable[2] = c_enable[1]&&q2&&!(q2%9);
    

    bcdcount counter0 (clk, reset, c_enable[0],q1/*, ... */);
    bcdcount counter1 (clk, reset, c_enable[1],q2/*, ... */);
    bcdcount counter2 (clk, reset, c_enable[2],q3/*, ... */);
    
    assign OneHertz=(c_enable[2]&&q3==3'b0&&q2==3'd9)?'b1:'b0; 

2个错误。 

错误原因：最后一行应该是4'd9...

module top_module (
    input clk,
    input reset,
    output OneHertz,
    output [2:0] c_enable
); //
    
    reg[3:0] q1,q2,q3;
    
    assign c_enable[0] ='b1;
    assign c_enable[1] = q1&&!(q1%9);
    assign c_enable[2] = c_enable[1]&&q2&&!(q2%9);
    

    bcdcount counter0 (clk, reset, c_enable[0],q1/*, ... */);
    bcdcount counter1 (clk, reset, c_enable[1],q2/*, ... */);
    bcdcount counter2 (clk, reset, c_enable[2],q3/*, ... */);
    
    assign OneHertz=(q1==4'd9&&q3==4'd9&&q2==4'd9)?'b1:'b0; 


endmodule

 success