[HDLBits] Exams/m2014 q4k

Implement the following circuit:

module top_module (
    input clk,
    input resetn,   // synchronous reset
    input in,
    output out);
    wire in1,in2,in3;
    parts part1(clk,resetn,in,in1);
    parts part2(clk,resetn,in1,in2);
    parts part3(clk,resetn,in2,in3);
    parts part4(clk,resetn,in3,out);
endmodule

module parts (
	input clk,
	input resetn,
    input d,
    output q);
    always@(posedge clk) begin
        if(!resetn)
            q<=0;
        else
            q<=d;
    end
endmodule