RISC-V (pronounced “risk-five”) is an open, free ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
The final user-level ISA specification, a draft compressed ISA specification, a draft privileged ISA specification, and a suite of RISC-V software tools including a GNU/GCC software tool chain, GNU/GDB debugger, an LLVM compiler, a Spike ISA simulator, QEMU, and a verification suite is available for download now.
To sample the architecture without installing anything, try out ANGEL, a JavaScript ISA simulator that boots an interactive session of riscv-linux on a simulated RISC-V machine in your browser.
RISC-V（发音为“Risk Five”）是一个开放的、自由的ISA，通过开放的标准协作实现了处理器创新的新时代。RISC-V ISA诞生于学术界和研究界，为未来50年的计算设计和创新铺平了道路。
最终的用户级ISA规范、一份压缩的ISA规范草案、一份特权ISA规范草案和一套RISC-V软件工具，包括GNU/GCC软件工具链、GNU/GDB调试器、LLVM编译器、SPICK ISA模拟器、QEMU和验证套件，现在可以下载。
要在不安装任何东西的情况下对体系结构进行采样，可以尝试Angel，一个JavaScript模拟器，它可以在浏览器中的一台模拟RISC-V机器上启动RISCVlinux的交互式会话。
You can also visit the UC Berkeley Architecture Research projects page to see a number of RISC-V based projects including a high-performance, energy-efficient Rocket processor (a 64-bit RISC-V single-issue in-order core), suitable for both high-speed simulation and full synthesis, is available for download.
Our intent is to provide a long-lived open ISA with significant infrastructure support, including documentation, compiler tool chains, operating system ports, reference software simulators, cycle-accurate FPGA emulators, high-performance FPGA computers, efficient ASIC implementations of various target platform designs, configurable processor generators, architecture test suites, and teaching materials.
您还可以访问加州大学伯克利分校建筑研究项目页面，查看一些基于RISC-V的项目，包括高性能、节能的火箭处理器（64位RISC-V单问题订单核心），适用于高速模拟和全合成，可供下载。
我们的目的是提供具有重要基础设施支持的长寿命开放式ISA，包括文档、编译器工具链、操作系统端口、参考软件模拟器、周期精确的FPGA模拟器、高性能FPGA计算机、各种目标平台设计的高效ASIC实现、可配置处理器generATORS、架构测试套件和教学材料
Key Features of the RISC-V ISA:
* Delivers a new level of software and hardware freedom on architecture in an open extensible way.
* Open ISA delivers easier support from a broad range of operating systems, software vendors and tool developers.
* The open source of hardware, RISC-V does not rely on a single supplier – offers multiple suppliers, therefore, supports unlimited potential for future growth.
* No other ISA is architected like the RISC-V ISA, allowing for user extensibility of the architecture without breaking existing extensions or incurring software fragmentation
RISC-V ISA的主要特点：
以开放的可扩展方式在体系结构上提供新的软件和硬件自由度。
开放式ISA提供了广泛操作系统、软件供应商和工具开发人员的更简单支持。
硬件的开放源代码RISC-V不依赖于单个供应商，它提供多个供应商，因此支持未来无限增长的潜力。
没有任何其他的ISA像RISC-V ISA那样架构化，允许用户在不破坏现有扩展或导致软件碎片化的情况下扩展该架构。
点击左侧的User-Level ISA Specification 进入新界面
Please note, RISC-V ISA and related specifications are developed, ratified and maintained by RISC-V Foundation contributing members within the RISC-V Foundation Technical Committee. Operating details of the Technical Committee can be found in the RISC-V Foundation Workspace. Work on the specification is performed on GitHub and the GitHub issue mechanism can be used to provide input into the specification.
The specifications shown below reflect the last official release. The most current version of the draft specification, which is in development within the Technical Committee, can be found here on GitHub.
请注意，RISC-V ISA和相关规范是由RISC-V基金会成员在RISC-V基金会技术委员会内制定、批准和维护的。技术委员会的操作细节可以在RISC-V基金会工作区找到。关于规范的工作是在GitHub上执行的，并且可以使用GitHub发布机制向规范提供输入。
下面显示的规范反映了上一次正式发布。技术委员会正在开发的最新版本的规范草案可以在Github上找到。