[HDLBits] Fsm ps2data

See also: PS/2 packet parser.

Now that you have a state machine that will identify three-byte messages in a PS/2 byte stream, add a datapath that will also output the 24-bit (3 byte) message whenever a packet is received (out_bytes[23:16] is the first byte, out_bytes[15:8] is the second byte, etc.).

out_bytes needs to be valid whenever the done signal is asserted. You may output anything at other times (i.e., don't-care).

module top_module(
    input clk,
    input [7:0] in,
    input reset,    // Synchronous reset
    output [23:0] out_bytes,
    output done); //
	//四个状态：没找到字节、找到第一个、第二个和第三个
    // State transition logic (combinational)
    reg [1:0] state,next;
    always@(*) begin
        case(state)
            0:next<=in[3]?1:0;
            1:next<=2;
            2:next<=3;
            3:next<=in[3]?1:0;
        endcase    
    end
    // State flip-flops (sequential)
    always@(posedge clk) begin
        if(reset)
            out_bytes<=24'b0;
        else begin
            case(state)
                //0:out_bytes<=24'b0;
                0:out_bytes[23:16]<=in;
                1:out_bytes[15:8]<=in;
                2:out_bytes[7:0]<=in;
                3:out_bytes[23:16]<=in;
                //反复写第一个字节，直到确认该字节有效
            endcase
        end
    end
    always@(posedge clk) begin
        if(reset)
            state<=0;
        else
            state<=next;
    end
    assign done=(state==3);
    // Output logic


    // New: Datapath to store incoming bytes.

endmodule