[HDLBits] Exams/ece241 2013 q8

Implement a Mealy-type finite state machine that recognizes the sequence "101" on an input signal named x. Your FSM should have an output signal, z, that is asserted to logic-1 when the "101" sequence is detected. Your FSM should also have an active-low asynchronous reset. You may only have 3 states in your state machine. Your FSM should recognize overlapping sequences.

module top_module (
    input clk,
    input aresetn,    // Asynchronous active-low reset
    input x,
    output z ); 
    //要求只有三个状态，识别101。这样的话应该要1结尾是一个状态，00和10分别一个状态。检测什么时候从10转101即可
    //这样因为只有结尾的1可能会被复用，所以把1结尾的合并即可
    reg [1:0]state,next;
    reg signal;
    parameter end_with_1=0,s10=1,s00=2;
    //把signal也判定一下
    always@(*) begin
        case(state)
            end_with_1:begin
                next<=x?end_with_1:s10;
                signal<=0;
            end
            s10:begin
                next<=x?end_with_1:s00;
                signal<=x?1:0;
            end
            s00:begin
                next<=x?end_with_1:s00;
                signal<=0;
            end
        endcase
    end
    always@(posedge clk or negedge aresetn) begin
        if(!aresetn)
            state<=s00;  //s00应该作为初始态
        else
            state<=next;
    end
    assign z=signal;
endmodule
//好好好，思路没问题。我太聪明了