HDLbits--Exams/2014 q3fsm

module top_module (
    input clk,
    input reset,   // Synchronous reset
    input s,
    input w,
    output z
);
    parameter a=0,b=1;
    reg state,next_state;
    
    always@(*)
        begin
            case(state)
                a:
                    next_state<=s?b:a;
                b:
                    next_state<=b;
            endcase
        end
    
    always@(posedge clk)
        begin
            if(reset)
                state<=a;
            else
                state<=next_state;
        end
    
    parameter b1=1,b2=2,b3=3;
    reg [1:0] statew,next;
    reg [2:0] temp;
    always@(*)
        begin
            if(state==b)
                begin
                    case(statew)
                        b1:
                            next<=b2;
                        b2:
                            next<=b3;
                        b3:
                            next<=b1;
                        default:
                            next<=b1;
                    endcase
                end
        end
    
    always@(posedge clk)
        begin
            if(statew==b1)
                temp[0]<=w;
            if(statew==b2)
                temp[1]<=w;
            if(statew==b3)
                temp[2]<=w;
        end
    
    always@(posedge clk)
        begin
            z<=(state==b3)&&(temp==3'b110||temp==3'b011||temp==3'b101);
        end
            
            
                
            
            
            
            
endmodule

正确答案：

module top_module (
    input clk,
    input reset,   // Synchronous reset
    input s,
    input w,
    output z
);
    parameter A = 0,B = 1,C = 2,D = 3;
    reg [1:0] count;
    reg [2:0] state,next_state;
   always @ (*)
        case (state)
            A: next_state = s?B:A;
            B: next_state = C;
            C: next_state = D;
            D: next_state = B;
            default next_state = A;
        endcase
    always @ (posedge clk)
        if (reset)
            state <= A;
    	else state <= next_state;
    always @ (posedge clk)
        case (state)
            B:count <= w ;
            C:count <= w ? count+1:count;
            D:begin count <= w ? count+1:count;  
                // count <= 1'b0;
            end
            default count <= 0;
        endcase
    assign z = ((state==B) && (count == 2) );   
            
            
                
            
            
            
            
endmodule