HDLbits: Fsm serial receiver and datapath answer

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output [7:0] out_byte,
    output done
); //

    // Use FSM from Fsm_serial
parameter start=3'b000, receive=3'b001, stop_r=3'b010, wat=3'b011, receive_f=3'b100, stop_w=3'b101;
    reg [2:0] state,next;
    reg [3:0] cnt;
    
    always @(*) begin
        case(state)
            start: 		next<=receive;
            receive:	next<=( cnt==4'd7 && in == 1) ? stop_r: ((cnt<4'd7) ? receive: receive_f);
            receive_f:  next<=(in) ? stop_w:receive_f;
            stop_r:		next<=(in) ? wat:start;
            stop_w:		next<=(in) ? wat:start;
            wat :		next<=(in) ? wat:start;
        endcase
    end
    
    always @(posedge clk) begin
        if(reset)
            state<=wat;
        else
            state<=next;
    end
    
    always @(posedge clk) begin
       	
        case(state)
            start:		cnt<=0;
            receive:	cnt<=cnt+1'b1;
            receive_f:	cnt<=cnt+1'b1;
            stop_r:		cnt<=0;
            stop_w:		cnt<=0;
            wat :		cnt<=0;
        endcase
    end
    
    assign done = ( state== stop_r);

    // New: Datapath to latch input bits.
        always @(posedge clk) begin
       	
            case(state)
                start  :    out_byte[0]<=in;
                receive:	out_byte[cnt+1]<=in;

        endcase
    end

endmodule