EDA17--PT脚本实例

前文已经介绍了使用PT进行STA的基本内容，接下来介绍两个实例进一步说明PT脚本的使用。和DC一样，一个同步fifo，一个异步FIFO。
最近才开始学写脚本，有很多写的不太好的地方，有问题还有指正，共同交流。

一、同步fifo

这是工作目录，可以看出有这么几个：
library用来放库文件，
pt_scripts用来放脚本，
report用来放输出时序报告，
results用来放输出sdf结果，
work是工作目录。
还有一个目录，是前一步DC输出的sdc文件，待会会有说明。现在打开pt_scripts目录，开始写脚本。

1、首先设置链接库和搜索路径。

#
#SETUP
#
set search_path             "/home/ICer/EDA/03_PT/fifo1/library"
set link_library            " * smic18_ff.db smic18_ss.db smic18_tt.db"
set_app_var link_library    " /$search_path/smic18_ss.db "

**2、设置一些路径，分别是输入路径、输出报告路径、输出结果路径、**关于输入路径可以查看博文链接: 链接: link

#
#Run_PT
#
set input_path      "/home/ICer/EDA/02_DC/fifo1/outputs"
set report_path     "/home/ICer/EDA/03_PT/fifo1/reports"
set result_path     "/home/ICer/EDA/03_PT/fifo1/results"
set DESIGN_NAME     "VR_FIFO"

3、读入网表文件设计，设置当前设计名。

#
# Read and link design
#
read_verilog        "/$input_path/VR_FIFO.v"
current_design      $DESIGN_NAME

4、设置工作环境。线负载模型

#
# Setting operating condition and min library
#
 set_operating_conditions -library smic18_ss worst
#set_operating_conditions -library smic18_ff best
set_wire_load_model      -library smic18_ss -name reference_area_20000

5、读入sdc约束文件

#
# Reading Constraints Section
#
read_sdc   -echo     " $input_path/VR_FIFO.sdc "

6、检查时序与输入报告和.sdf文件。

update_timing
check_timing                    > ../reports/${DESIGN_NAME}_check_timing_typical.rpt

# *********************************************************
#  Report timing
# *********************************************************
report_global_timing            > ../reports/${DESIGN_NAME}_report_global_timing_typical.report
report_clock -skew -attribute   > ../reports/${DESIGN_NAME}_report_clock_typical.report 
report_analysis_coverage        > ../reports/${DESIGN_NAME}_report_analysis_coverage_typical.report
report_timing -slack_lesser_than 0.0 -delay min_max -nosplit -input -net  > ../reports/${DESIGN_NAME}_report_timing_typical.report

# *********************************************************
#  Generate SDF file for simulation
# *********************************************************
write_sdf -context Verilog        ../results/${DESIGN_NAME}_typical.sdf

总体上同步fifo脚本设计如下：

#
#SETUP
#
set search_path             "/home/ICer/EDA/03_PT/fifo1/library"
set link_library            " * smic18_ff.db smic18_ss.db smic18_tt.db"
set_app_var link_library    " /$search_path/smic18_ss.db "

#
#Run_PT
#
set input_path      "/home/ICer/EDA/02_DC/fifo1/outputs"
set report_path     "/home/ICer/EDA/03_PT/fifo1/reports"
set result_path     "/home/ICer/EDA/03_PT/fifo1/results"
set DESIGN_NAME     "VR_FIFO"

#
# Read and link design
#
read_verilog        "/$input_path/VR_FIFO.v"
current_design      $DESIGN_NAME

#
# Setting operating condition and min library
#
 set_operating_conditions -library smic18_ss worst
#set_operating_conditions -library smic18_ff best
set_wire_load_model      -library smic18_ss -name reference_area_20000


#
# Reading Constraints Section
#
read_sdc   -echo     " $input_path/VR_FIFO.sdc "

#
#    Back Annotation Section 
#
read_sdf             " $input_path/VR_FIFO.sdf "

#
#  Update / check timing
#

update_timing
check_timing                    > ../reports/${DESIGN_NAME}_check_timing_typical.rpt

# *********************************************************
#  Report timing
# *********************************************************
report_global_timing            > ../reports/${DESIGN_NAME}_report_global_timing_typical.report
report_clock -skew -attribute   > ../reports/${DESIGN_NAME}_report_clock_typical.report 
report_analysis_coverage        > ../reports/${DESIGN_NAME}_report_analysis_coverage_typical.report
report_timing -slack_lesser_than 0.0 -delay min_max -nosplit -input -net  > ../reports/${DESIGN_NAME}_report_timing_typical.report

# *********************************************************
#  Generate SDF file for simulation
# *********************************************************
write_sdf -context Verilog        ../results/${DESIGN_NAME}_typical.sdf

二、异步fifo

工作目录和同步一样，脚本思路一样，具体如下：

ch_path  [list /home/ICer/EDA/03_PT/fifo2/library]
set_app_var link_library               [list {*} smic18_ss.db]

#set_app_var sh_command_log_file  "command.log"
#set_app_var sh_continue_on_error "false"
#set_app_var report_default_significant_digits 3
#set_app_var sh_source_uses_search_path true
#
#Run_PT
#
set input_path      "/home/ICer/EDA/02_DC/fifo2/outputs"
set report_path     "/home/ICer/EDA/03_PT/fifo2/reports"
set result_path     "/home/ICer/EDA/03_PT/fifo2/results"
set DESIGN_NAME     "fifo"

#
# Read and link design
#
read_verilog        "/$input_path/fifo.v"


current_design      $DESIGN_NAME
link


#
# Setting operating condition and min library
#
 set_operating_conditions -library smic18_ss worst
#set_operating_conditions -library smic18_ff best
set_wire_load_model      -library smic18_ss -name reference_area_20000

#
# Reading Constraints Section
#
read_sdc            " $input_path/fifo.sdc "

#
#  Update / check timing
#

set_app_var timing_report_unconstrained_paths true



update_timing
check_timing                    > ../reports/${DESIGN_NAME}_check_timing_typical.rpt

# *********************************************************
#  Report timing
# *********************************************************
report_global_timing            > ../reports/${DESIGN_NAME}_report_global_timing_typical.report
report_clock -skew -attribute   > ../reports/${DESIGN_NAME}_report_clock_typical.report 
report_analysis_coverage        > ../reports/${DESIGN_NAME}_report_analysis_coverage_typical.report
report_timing -slack_lesser_than 0.0 -delay min_max -nosplit -input -net  > ../reports/${DESIGN_NAME}_report_timing_typical.report

# *********************************************************
#  Generate SDF file for simulation
# *********************************************************
write_sdf -context Verilog        ../results/${DESIGN_NAME}_typical.sdf

三、操作示例

以异步FIFO为例，
1、首先打开work目录，终端打开，
2、输入pt_shell,进入pt工作目录
这里有个error，不管。
3、输入指令：source -e -v ../pt_scripts/fifo2_pt.tcl
4、输入检查时序：report_timing

5、读入sdf 反标文件，read_sdf /$input_path/fifo.sdf
6、再次查看时序检查。

其中带有*的是被sdf文件反标的路径信息。
slack满足时序要求。完成。