Exams/2014 q3bfsm

Given the state-assigned table shown below, implement the finite-state machine. Reset should reset the FSM to state 000

 

module top_module (
    input clk,
    input reset,   // Synchronous reset
    input x,
    output z
);
    reg [2:0]state,next_state;
    parameter a=3'b000;
    parameter b=3'b001;
    parameter c=3'b010;
    parameter d=3'b011;
    parameter e=3'b100;
    
    
    always@(posedge clk)begin
        if(reset)
            state<=a;
    else
        state<=next_state;
    end
    
    always@(*)begin
        case(state)
            a:next_state<=x?b:a;
            b:next_state<=x?e:b;
            c:next_state<=x?b:c;
            d:next_state<=x?c:b;
            e:next_state<=x?e:d;
          default:next_state<=a;
        endcase
      
    end
    
    assign z=(state==d | state==e);
    

endmodule