10.26数字钟设计，数电第二次实验总结
实验七 数字钟设计（*****）
实现一个六十进制数字时钟，秒到 60 则归零重加，同时让分加1，分加到60归零重加，并让小时加 1，小时加到24归零重加。要求用数码管1,0显示秒值，数码管3,2显示分值，小时以十六进制形式显示在led灯上。
文件结构
顶层文件
`timescale 1ns / 1ps
module total(
input clk,//开关，开时复位
input reset,
output[6:0]show,//表示怎么亮
output[3:0]dn0,//表示4个数码管哪个亮
output[7:0] hour//表示下面LED的情况
);//最后输出就是这三个信号
wire[3:0]minh;
wire[3:0]minl;
wire[3:0]sech;
wire[3:0]secl;
pclock pc(clk,reset,minh,minl,sech,secl,hour);
show ps(clk,reset,minh,minl,sech,secl,show,dn0);//将out0~3信号处理为数码管信号
endmodule产生时钟信号
`timescale 1ns / 1ps
module pclock(
input clk,
input reset,
output reg[3:0]minh,
output reg[3:0]minl,
output reg[3:0]sech,
output reg[3:0]secl,
output reg[7:0]hour
);//产生时分秒信号
wire hzone;
hz1 u(clk,hzone);
//产生秒的低位
always@(posedge hzone,negedge reset)begin
if(!reset)begin
secl=0;
end
else begin
if(secl==9)
secl<=0;
else
secl<=secl+1'b1;
end
end
//秒的高位
always@(negedge secl[3],negedge reset)begin
if(!reset)
sech=0;
else begin
if(sech==5)
sech<=0;
else
sech<=sech+1'b1;
end
end
//分的低位
always@(negedge sech[2],negedge reset)begin
if(!reset)
minl=0;
else begin
if(minl==9)
minl<=0;
else
minl<=minl+1'b1;
end
end
//分的高位
always@(negedge minl[3],negedge reset)begin
if(!reset)
minh=0;
else begin
if(minh==5)
minh<=0;
else
minh<=minh+1'b1;
end
end
//小时
always@(negedge minh[2],negedge reset)begin
if(!reset)
hour=0;
else
hour<=hour+1'b1;
end
endmodule
分频器1
`timescale 1ns / 1ps
module hz1(
input clk,
output reg clk_o
);//将系统时钟处理为1HZ信号
reg[31:0]cnt;
parameter n=99999999;
always@(posedge clk)begin
if(cnt==9999999)
cnt=0;
else begin
cnt=cnt+1'b1;
if(cnt<=49999999)
clk_o=1'b1;
else
clk_o=1'b0;
end
end
endmodule
显示分秒
`timescale 1ns / 1ps
module show(
input clk,
input reset,
input[3:0]minh,
input[3:0]minl,
input[3:0]sech,
input[3:0]secl,
output reg[6:0]show,
output reg [3:0] en
);//显示时分秒信号，选择出一个信号
//将最终选择出的要显示信号转化为数码管信号
wire hzshow;
showhz v(clk,hzshow);
//四位数码管，高位分（6进制，3位）低位分（10进制，4位）高位秒低位秒，共要14位,统一都成四位
reg[3:0]digit;
//确定数码管显示的第几位
reg[1:0]dn;
always@(posedge hzshow,negedge reset)begin
if(!reset)
dn<=0;
else begin
if(dn==3)
dn<=0;
else
dn<=dn+1'b1;
end
end
//确定位上的数字
always@(dn, reset)begin
if(!reset)begin
digit<=0;
en<=4'b0000;
end
else begin
case(dn)
0: begin en <= 4'b1110; digit<=secl; end
1: begin en <= 4'b1101; digit<=sech; end
2: begin en <= 4'b1011; digit<=minl; end
3: begin en <= 4'b0111; digit<=minh; end
endcase
end
end
//将其转化为数码管信号
always@(digit, reset) begin
if(!reset)
show = 7'b0000001;
else begin
case(digit)
4'h0: show <= 7'b0000001;
4'h1: show <= 7'b1001111;
4'h2: show <= 7'b0010010;
4'h3: show <= 7'b0000110;
4'h4: show <= 7'b1001100;
4'h5: show <= 7'b0100100;
4'h6: show <= 7'b0100000;
4'h7: show <= 7'b0001111;
4'h8: show <= 7'b0000000;
4'h9: show <= 7'b0000100;
endcase
end
end
endmodule
分频器2
`timescale 1ns / 1ps
module showhz(
input clk,
output reg clk_o
);//将系统时钟处理为1HZ信号
reg[31:0]cnt;
always@(posedge clk)begin
if(cnt==99999)
cnt=0;
else begin
cnt=cnt+1'b1;
if(cnt<=49999)
clk_o=1'b1;
else
clk_o=1'b0;
end
end
endmodule
引脚文件
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets reset_IBUF]
set_property PACKAGE_PIN R2 [get_ports reset]
set_property IOSTANDARD LVCMOS33 [get_ports reset]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports {show[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {show[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {show[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {show[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {show[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {show[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {show[0]}]
set_property PACKAGE_PIN U7 [get_ports {show[0]}]
set_property PACKAGE_PIN V5 [get_ports {show[1]}]
set_property PACKAGE_PIN U5 [get_ports {show[2]}]
set_property PACKAGE_PIN V8 [get_ports {show[3]}]
set_property PACKAGE_PIN U8 [get_ports {show[4]}]
set_property PACKAGE_PIN W6 [get_ports {show[5]}]
set_property PACKAGE_PIN W7 [get_ports {show[6]}]
set_property PACKAGE_PIN U2 [get_ports {dn0[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dn0[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dn0[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dn0[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dn0[0]}]
set_property PACKAGE_PIN U4 [get_ports {dn0[1]}]
set_property PACKAGE_PIN V4 [get_ports {dn0[2]}]
set_property PACKAGE_PIN W4 [get_ports {dn0[3]}]
set_property PACKAGE_PIN W15 [get_ports {hour[7]}]
set_property PACKAGE_PIN W13 [get_ports {hour[6]}]
set_property PACKAGE_PIN W14 [get_ports {hour[5]}]
set_property PACKAGE_PIN U15 [get_ports {hour[4]}]
set_property PACKAGE_PIN U16 [get_ports {hour[3]}]
set_property PACKAGE_PIN V13 [get_ports {hour[2]}]
set_property PACKAGE_PIN V14 [get_ports {hour[1]}]
set_property PACKAGE_PIN U14 [get_ports {hour[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {hour[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {hour[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {hour[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {hour[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {hour[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {hour[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {hour[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {hour[0]}]
set_property PACKAGE_PIN W5 [get_ports clk]