stc8xxxx.h

/*------------------------------------------------------------------*/
/* --- STC MCU International Limited -------------------------------*/
/* --- STC 1T Series MCU RC Demo -----------------------------------*/
/* --- Mobile: (86)13922805190 -------------------------------------*/
/* --- Fax: 86-0513-55012956,55012947,55012969 ---------------------*/
/* --- Tel: 86-0513-55012928,55012929,55012966 ---------------------*/
/* --- Web: www.GXWMCU.com -----------------------------------------*/
/* --- QQ:  800003751 ----------------------------------------------*/
/* If you want to use the program or the program referenced in the  */
/* article, please specify in which data and procedures from STC    */
/*------------------------------------------------------------------*/



#ifndef	_STC8xxxx_H
#define	_STC8xxxx_H

#include 

/*  BYTE Registers  */
sfr P0    = 0x80;
sfr SP    = 0x81;
sfr DPL   = 0x82;
sfr DPH   = 0x83;
sfr	S4CON = 0x84;
sfr	S4BUF = 0x85;
sfr PCON  = 0x87;

sfr TCON = 0x88;
sfr TMOD = 0x89;
sfr TL0  = 0x8A;
sfr TL1  = 0x8B;
sfr TH0  = 0x8C;
sfr TH1  = 0x8D;
sfr	AUXR = 0x8E;
sfr WAKE_CLKO = 0x8F;
sfr INT_CLKO  = 0x8F;

sfr P1    = 0x90;
sfr P1M1  = 0x91;	//P1M1.n,P1M0.n 	=00--->Standard,	01--->push-pull		ʵ¼ÊÉÏ1TµÄ¶¼Ò»Ñù
sfr P1M0  = 0x92;	//					=10--->pure input,	11--->open drain
sfr P0M1  = 0x93;	//P0M1.n,P0M0.n 	=00--->Standard,	01--->push-pull
sfr P0M0  = 0x94;	//					=10--->pure input,	11--->open drain
sfr P2M1  = 0x95;	//P2M1.n,P2M0.n 	=00--->Standard,	01--->push-pull
sfr P2M0  = 0x96;	//					=10--->pure input,	11--->open drain
sfr PCON2 = 0x97;
sfr	AUXR2 = 0x97;

sfr SCON  = 0x98;
sfr SBUF  = 0x99;
sfr S2CON = 0x9A;	//
sfr S2BUF = 0x9B;	//

sfr P2    = 0xA0;
sfr BUS_SPEED = 0xA1;
sfr AUXR1 = 0xA2;
sfr P_SW1 = 0xA2;

sfr IE    = 0xA8;
sfr SADDR = 0xA9;
sfr WKTCL = 0xAA;	//»½ÐѶ¨Ê±Æ÷µÍ×Ö½Ú
sfr WKTCH = 0xAB;	//»½ÐѶ¨Ê±Æ÷¸ß×Ö½Ú
sfr	S3CON = 0xAC;
sfr S3BUF = 0xAD;
sfr TA    = 0xAE;
sfr IE2   = 0xAF;	//STC12C5A60S2ϵÁÐ

sfr P3    = 0xB0;
sfr P3M1  = 0xB1;	//P3M1.n,P3M0.n 	=00--->Standard,	01--->push-pull
sfr P3M0  = 0xB2;	//					=10--->pure input,	11--->open drain
sfr P4M1  = 0xB3;	//P4M1.n,P4M0.n 	=00--->Standard,	01--->push-pull
sfr P4M0  = 0xB4;	//					=10--->pure input,	11--->open drain
sfr IP2   = 0xB5;	//STC12C5A60S2ϵÁÐ
sfr IP2H  = 0xB6;	//STC12C5A60S2ϵÁÐ
sfr IPH   = 0xB7;

sfr IP        = 0xB8;
sfr SADEN     = 0xB9;
sfr	P_SW2     = 0xBA;
sfr	VOCTRL    = 0xBB;
sfr ADC_CONTR = 0xBC;	//ADC¿ØÖƼĴæÆ÷
sfr ADC_RES   = 0xBD;	//ADC½á¹û¸ß×Ö½Ú
sfr ADC_RESL  = 0xBE;	//ADC½á¹ûµÍ×Ö½Ú

sfr P4        = 0xC0;
sfr WDT_CONTR = 0xC1;

sfr IAP_DATA  = 0xC2;
sfr IAP_ADDRH = 0xC3;
sfr IAP_ADDRL = 0xC4;
sfr IAP_CMD   = 0xC5;
sfr IAP_TRIG  = 0xC6;
sfr IAP_CONTR = 0xC7;

sfr ISP_DATA  = 0xC2;
sfr ISP_ADDRH = 0xC3;
sfr ISP_ADDRL = 0xC4;
sfr ISP_CMD   = 0xC5;
sfr ISP_TRIG  = 0xC6;
sfr ISP_CONTR = 0xC7;

sfr P5     = 0xC8;	//
sfr P5M1   = 0xC9;	//	P5M1.n,P5M0.n 	=00--->Standard,	01--->push-pull
sfr P5M0   = 0xCA;	//					=10--->pure input,	11--->open drain
sfr P6M1   = 0xCB;	//	P5M1.n,P5M0.n 	=00--->Standard,	01--->push-pull
sfr P6M0   = 0xCC;	//					=10--->pure input,	11--->open drain
sfr SPSTAT = 0xCD;	//
sfr SPCTL  = 0xCE;	//
sfr SPDAT  = 0xCF;	//

sfr PSW    = 0xD0;
sfr	T4T3M  = 0xD1;
sfr	T4H    = 0xD2;
sfr	T4L    = 0xD3;
sfr	T3H    = 0xD4;
sfr	T3L    = 0xD5;
sfr	T2H    = 0xD6;
sfr	T2L    = 0xD7;

sfr	TH4    = 0xD2;
sfr	TL4    = 0xD3;
sfr	TH3    = 0xD4;
sfr	TL3    = 0xD5;
sfr	TH2    = 0xD6;
sfr	TL2    = 0xD7;

sfr CCON   = 0xD8;	//
sfr CMOD   = 0xD9;	//
sfr CCAPM0 = 0xDA;	//PCAÄ£¿é0µÄ¹¤×÷ģʽ¼Ä´æÆ÷¡£
sfr CCAPM1 = 0xDB;	//PCAÄ£¿é1µÄ¹¤×÷ģʽ¼Ä´æÆ÷¡£
sfr CCAPM2 = 0xDC;	//PCAÄ£¿é2µÄ¹¤×÷ģʽ¼Ä´æÆ÷¡£
sfr CCAPM3 = 0xDD;	//PCAÄ£¿é3µÄ¹¤×÷ģʽ¼Ä´æÆ÷¡£
sfr	ADCCFG = 0xDE;	//

sfr ACC    = 0xE0;
sfr	P7M1   = 0xE1;
sfr	P7M0   = 0xE2;
sfr	DPS    = 0xE3;
sfr	DPL1   = 0xE4;
sfr	DPH1   = 0xE5;
sfr	CMPCR1 = 0xE6;
sfr	CMPCR2 = 0xE7;

sfr	P6     = 0xE8;
sfr CL     = 0xE9;	//
sfr CCAP0L = 0xEA;	//PCAÄ£¿é0µÄ²¶×½/±È½Ï¼Ä´æÆ÷µÍ8λ¡£
sfr CCAP1L = 0xEB;	//PCAÄ£¿é1µÄ²¶×½/±È½Ï¼Ä´æÆ÷µÍ8λ¡£
sfr CCAP2L = 0xEC;	//PCAÄ£¿é2µÄ²¶×½/±È½Ï¼Ä´æÆ÷µÍ8λ¡£
sfr CCAP3L = 0xED;	//PCAÄ£¿é3µÄ²¶×½/±È½Ï¼Ä´æÆ÷µÍ8λ¡£
sfr	AUXINTIF = 0xEF;	//¸¨ÖúÖжϱêÖ¾ B6-INT4IF, B5-INT3IF, B4-INT2IF, B2-T4IF, B1-T3IF, B0-T2IF

sfr B        = 0xF0;
sfr	PWMCFG   = 0xF1;	//PWMÅäÖüĴæÆ÷
sfr PCA_PWM0 = 0xF2;	//PCAÄ£¿é0 PWM¼Ä´æÆ÷¡£
sfr PCA_PWM1 = 0xF3;	//PCAÄ£¿é1 PWM¼Ä´æÆ÷¡£
sfr PCA_PWM2 = 0xF4;	//PCAÄ£¿é2 PWM¼Ä´æÆ÷¡£
sfr PCA_PWM3 = 0xF5;	//PCAÄ£¿é3 PWM¼Ä´æÆ÷¡£
sfr	PWMIF    = 0xF6;	//PWMÖжϱêÖ¾¼Ä´æÆ÷
sfr	PWMFDCR  = 0xF7;	//PWMÍⲿÒì³£¿ØÖƼĴæÆ÷

sfr	P7     = 0xF8;
sfr CH     = 0xF9;
sfr CCAP0H = 0xFA;		//PCAÄ£¿é0µÄ²¶×½/±È½Ï¼Ä´æÆ÷¸ß8λ¡£
sfr CCAP1H = 0xFB;		//PCAÄ£¿é1µÄ²¶×½/±È½Ï¼Ä´æÆ÷¸ß8λ¡£
sfr CCAP2H = 0xFC;		//PCAÄ£¿é2µÄ²¶×½/±È½Ï¼Ä´æÆ÷¸ß8λ¡£
sfr CCAP3H = 0xFD;		//PCAÄ£¿é3µÄ²¶×½/±È½Ï¼Ä´æÆ÷¸ß8λ¡£
sfr	PWMCR  = 0xFE;		//PWM¿ØÖƼĴæÆ÷
sfr	RSTCFG = 0xFF;		//


//                                     7    6    5    4    3     2       1       0      Reset Value
//INT_CLKO:  ÖжÏÓëʱÖÓÊä³ö¿ØÖƼĴæÆ÷  -   EX4  EX3  EX2   -   T2CLKO  T1CLKO  T0CLKO    0000,0000
#define	INT4_Enable()	INT_CLKO |= (1 << 6)
#define	INT3_Enable()	INT_CLKO |= (1 << 5)	
#define	INT2_Enable()	INT_CLKO |= (1 << 4)	
#define	INT1_Enable()	EX1 = 1
#define	INT0_Enable()	EX0 = 1

#define	INT4_Disable()	INT_CLKO &= ~(1 << 6)
#define	INT3_Disable()	INT_CLKO &= ~(1 << 5)	
#define	INT2_Disable()	INT_CLKO &= ~(1 << 4)	
#define	INT1_Disable()	EX1 = 0
#define	INT0_Disable()	EX0 = 0

//                               7    6       5       4      3    2     1     0      Reset Value
//AUXINTIF:  ¸¨ÖúÖжϱêÖ¾¼Ä´æÆ÷  -  INT4IF  INT3IF  INT2IF   -   T4IF  T3IF  T2IF    0000,0000
#define	INT4IF	0x40
#define	INT3IF	0x20
#define	INT2IF	0x10
#define	T4IF	0x04
#define	T3IF	0x02
#define	T2IF	0x01

#define	INT4_Clear()	AUXINTIF &= ~INT4IF		/* Çå³ýÍâÖжÏ4±ê־λ */
#define	INT3_Clear()	AUXINTIF &= ~INT3IF		/* Çå³ýÍâÖжÏ3±ê־λ */
#define	INT2_Clear()	AUXINTIF &= ~INT2IF		/* Çå³ýÍâÖжÏ2±ê־λ */
#define	INT1_Clear()	IE1 = 0					/* Çå³ýÍâÖжÏ1±ê־λ */
#define	INT0_Clear()	IE0 = 0					/* Çå³ýÍâÖжÏ0±ê־λ */

#define	INT0_Fall()		IT0 = 1		/* INT0 ϽµÑØÖÐ¶Ï           */
#define	INT0_RiseFall()	IT0 = 0		/* INT0 ϽµÑØÉÏÉýÑؾùÖÐ¶Ï   */
#define	INT1_Fall()		IT1 = 1		/* INT1 ϽµÑØÖÐ¶Ï           */
#define	INT1_RiseFall()	IT0 = 0		/* INT1 ϽµÑØÉÏÉýÑؾùÖÐ¶Ï   */


//===============================================================
#define	EAXSFR()		P_SW2 |=  0x80		/* MOVX A,@DPTR/MOVX @DPTR,AÖ¸ÁîµÄ²Ù×÷¶ÔÏóΪÀ©Õ¹SFR(XSFR) */
#define	EAXRAM()		P_SW2 &= ~0x80		/* MOVX A,@DPTR/MOVX @DPTR,AÖ¸ÁîµÄ²Ù×÷¶ÔÏóΪÀ©Õ¹RAM(XRAM) */

#define CLKSEL      (*(unsigned char volatile xdata *)0xfe00)
#define	CKSEL		(*(unsigned char volatile xdata *)0xfe00)	/* Ö÷ʱÖÓÔ´Ñ¡Ôñ    */
#define	CLKDIV		(*(unsigned char volatile xdata *)0xfe01)	/* Ö÷ʱÖÓ·ÖƵ      */
#define	IRC24MCR	(*(unsigned char volatile xdata *)0xfe02)	/* IRC 24MHZ¿ØÖÆ   */
#define	XOSCCR		(*(unsigned char volatile xdata *)0xfe03)	/* XOSC¿ØÖÆ        */
#define	IRC32KCR	(*(unsigned char volatile xdata *)0xfe04)	/* IRC 32KHZ¿ØÖÆ   */

#define	MainFosc_IRC24M()	CKSEL = (CKSEL & ~0x03)			/* Ñ¡ÔñÄÚ²¿24MHZʱÖÓ */
#define	MainFosc_XTAL()		CKSEL = (CKSEL & ~0x03) | 0x01	/* Ñ¡ÔñÍⲿ¾§Õñ»òʱÖÓ */
#define	EXT_CLOCK()			XOSCCR = 0x80					/* Ñ¡ÔñÍⲿʱÖÓ */
#define	EXT_CRYSTAL()		XOSCCR = 0xC0					/* Ñ¡ÔñÍⲿ¾§Õñ */
#define	MainFosc_IRC32K()	CKSEL =  CKSEL | 0x03			/* Ñ¡ÔñÄÚ²¿32KʱÖÓ */
#define	MainFosc_OutP54()	CKSEL = (CKSEL & ~0x08)			/* ´ÓP5.4Êä³öÖ÷ʱÖÓ·ÖƵ */
#define	MainFosc_OutP16()	CKSEL = (CKSEL |  0x08)			/* ´ÓP1.6Êä³öÖ÷ʱÖÓ·ÖƵ */
#define	MCLKO_None()		CKSEL = (CKSEL &  0x0f)			/* Ö÷ʱÖÓ²»Êä³ö 	*/
#define	MCLKO_DIV1()		CKSEL = (CKSEL &  0x0f) | 0x10	/* Ö÷ʱÖÓ1·ÖƵÊä³ö */
#define	MCLKO_DIV2()		CKSEL = (CKSEL &  0x0f) | 0x20	/* Ö÷ʱÖÓ2·ÖƵÊä³ö  */
#define	MCLKO_DIV4()		CKSEL = (CKSEL &  0x0f) | 0x40	/* Ö÷ʱÖÓ4·ÖƵÊä³ö  */
#define	MCLKO_DIV8()		CKSEL = (CKSEL &  0x0f) | 0x60	/* Ö÷ʱÖÓ8·ÖƵÊä³ö  */
#define	MCLKO_DIV16()		CKSEL = (CKSEL &  0x0f) | 0x80	/* Ö÷ʱÖÓ16·ÖƵÊä³ö  */
#define	MCLKO_DIV32()		CKSEL = (CKSEL &  0x0f) | 0xa0	/* Ö÷ʱÖÓ32·ÖƵÊä³ö  */
#define	MCLKO_DIV64()		CKSEL = (CKSEL &  0x0f) | 0xc0	/* Ö÷ʱÖÓ64·ÖƵÊä³ö  */
#define	MCLKO_DIV128()		CKSEL = (CKSEL &  0x0f) | 0xe0	/* Ö÷ʱÖÓ128·ÖƵÊä³ö  */

#define	MCLKO_P54	0x00	/* ´ÓP5.4Êä³öÖ÷ʱÖÓ·ÖƵ */
#define	MCLKO_P16	0x08	/* ´ÓP1.6Êä³öÖ÷ʱÖÓ·ÖƵ */
#define	MCLKO_0		0x00	/* Ö÷ʱÖÓ²»Êä³ö 	*/
#define	MCLKO_1		0x10	/* Ö÷ʱÖÓ1·ÖƵÊä³ö */
#define	MCLKO_2		0x20	/* Ö÷ʱÖÓ2·ÖƵÊä³ö  */
#define	MCLKO_4		0x40	/* Ö÷ʱÖÓ4·ÖƵÊä³ö  */
#define	MCLKO_8		0x60	/* Ö÷ʱÖÓ8·ÖƵÊä³ö  */
#define	MCLKO_16	0x80	/* Ö÷ʱÖÓ16·ÖƵÊä³ö  */
#define	MCLKO_32	0xa0	/* Ö÷ʱÖÓ32·ÖƵÊä³ö  */
#define	MCLKO_64	0xc0	/* Ö÷ʱÖÓ64·ÖƵÊä³ö  */
#define	MCLKO_128	0xe0	/* Ö÷ʱÖÓ128·ÖƵÊä³ö  */


#define	P0PU		(*(unsigned char volatile xdata *)0xfe10)	/* P0 1.5K Pull Up Enable  */
#define	P1PU		(*(unsigned char volatile xdata *)0xfe11)	/* P1 1.5K Pull Up Enable  */
#define	P2PU		(*(unsigned char volatile xdata *)0xfe12)	/* P2 1.5K Pull Up Enable  */
#define	P3PU		(*(unsigned char volatile xdata *)0xfe13)	/* P3 1.5K Pull Up Enable  */
#define	P4PU		(*(unsigned char volatile xdata *)0xfe14)	/* P4 1.5K Pull Up Enable  */
#define	P5PU		(*(unsigned char volatile xdata *)0xfe15)	/* P5 1.5K Pull Up Enable  */
#define	P6PU		(*(unsigned char volatile xdata *)0xfe16)	/* P6 1.5K Pull Up Enable  */
#define	P7PU		(*(unsigned char volatile xdata *)0xfe17)	/* P7 1.5K Pull Up Enable  */

#define	P0NCS		(*(unsigned char volatile xdata *)0xfe18)	/* P0 Non Schmit Trigger  */
#define	P1NCS		(*(unsigned char volatile xdata *)0xfe19)	/* P1 Non Schmit Trigger  */
#define	P2NCS		(*(unsigned char volatile xdata *)0xfe1a)	/* P2 Non Schmit Trigger  */
#define	P3NCS		(*(unsigned char volatile xdata *)0xfe1b)	/* P3 Non Schmit Trigger  */
#define	P4NCS		(*(unsigned char volatile xdata *)0xfe1c)	/* P4 Non Schmit Trigger  */
#define	P5NCS		(*(unsigned char volatile xdata *)0xfe1d)	/* P5 Non Schmit Trigger  */
#define	P6NCS		(*(unsigned char volatile xdata *)0xfe1e)	/* P6 Non Schmit Trigger  */
#define	P7NCS		(*(unsigned char volatile xdata *)0xfe1f)	/* P7 Non Schmit Trigger  */

#define	I2CCFG		(*(unsigned char volatile xdata *)0xfe80)	/*   */
#define	I2CMSCR		(*(unsigned char volatile xdata *)0xfe81)	/*   */
#define	I2CMSST		(*(unsigned char volatile xdata *)0xfe82)	/*   */
#define	I2CSLCR		(*(unsigned char volatile xdata *)0xfe83)	/*   */
#define	I2CSLST		(*(unsigned char volatile xdata *)0xfe84)	/*   */
#define	I2CSLADR	(*(unsigned char volatile xdata *)0xfe85)	/*   */
#define	I2CTXD		(*(unsigned char volatile xdata *)0xfe86)	/*   */
#define	I2CRXD		(*(unsigned char volatile xdata *)0xfe87)	/*   */

#define PWM0T1      (*(unsigned int  volatile xdata *)0xff00)
#define PWM0T2      (*(unsigned int  volatile xdata *)0xff02)
#define PWM1T1      (*(unsigned int  volatile xdata *)0xff10)
#define PWM1T2      (*(unsigned int  volatile xdata *)0xff12)
#define PWM2T1      (*(unsigned int  volatile xdata *)0xff20)
#define PWM2T2      (*(unsigned int  volatile xdata *)0xff22)
#define PWM3T1      (*(unsigned int  volatile xdata *)0xff30)
#define PWM3T2      (*(unsigned int  volatile xdata *)0xff32)
#define PWM4T1      (*(unsigned int  volatile xdata *)0xff40)
#define PWM4T2      (*(unsigned int  volatile xdata *)0xff42)
#define PWM5T1      (*(unsigned int  volatile xdata *)0xff50)
#define PWM5T2      (*(unsigned int  volatile xdata *)0xff52)
#define PWM6T1      (*(unsigned int  volatile xdata *)0xff60)
#define PWM6T2      (*(unsigned int  volatile xdata *)0xff62)
#define PWM7T1      (*(unsigned int  volatile xdata *)0xff70)        
#define PWM7T2      (*(unsigned int  volatile xdata *)0xff72)
#define PWMC        (*(unsigned int  volatile xdata *)0xfff0)
#define TADCP      	(*(unsigned int  volatile xdata *)0xfff3)	/* ÔÚ ETADC==1 µÄÇé¿öÏÂ,  ÿһ¸öÖÜÆÚÖÐ, µ±Counter¼ÆÊýµ½ TADCP[15:0] ʱ,×Ô¶¯Æô¶¯ ADC */

#define PWM0T1H     (*(unsigned char volatile xdata *)0xff00)	/* PWM0T1¼ÆÊý¸ß×Ö½Ú */
#define PWM0T1L     (*(unsigned char volatile xdata *)0xff01)	/* PWM0T1¼ÆÊýµÍ×Ö½Ú */
#define PWM0T2H     (*(unsigned char volatile xdata *)0xff02)	/* PWM0T2¼ÆÊý¸ß×Ö½Ú */
#define PWM0T2L     (*(unsigned char volatile xdata *)0xff03)	/* PWM0T2¼ÆÊýµÍ×Ö½Ú */
#define PWM0CR      (*(unsigned char volatile xdata *)0xff04)	/* PWM0¿ØÖÆ         */
#define PWM0HLD     (*(unsigned char volatile xdata *)0xff05)	/*          */

#define PWM1T1H     (*(unsigned char volatile xdata *)0xff10)	/* PWM1T1¼ÆÊý¸ß×Ö½Ú */
#define PWM1T1L     (*(unsigned char volatile xdata *)0xff11)	/* PWM1T1¼ÆÊýµÍ×Ö½Ú */
#define PWM1T2H     (*(unsigned char volatile xdata *)0xff12)	/* PWM1T2¼ÆÊý¸ß×Ö½Ú */
#define PWM1T2L     (*(unsigned char volatile xdata *)0xff13)	/* PWM1T2¼ÆÊýµÍ×Ö½Ú */
#define PWM1CR      (*(unsigned char volatile xdata *)0xff14)	/* PWM1¿ØÖÆ         */
#define PWM1HLD     (*(unsigned char volatile xdata *)0xff15)	/*          */

#define PWM2T1H     (*(unsigned char volatile xdata *)0xff20)	/* PWM2T1¼ÆÊý¸ß×Ö½Ú */
#define PWM2T1L     (*(unsigned char volatile xdata *)0xff21)	/* PWM2T1¼ÆÊýµÍ×Ö½Ú */
#define PWM2T2H     (*(unsigned char volatile xdata *)0xff22)	/* PWM2T2¼ÆÊý¸ß×Ö½Ú */
#define PWM2T2L     (*(unsigned char volatile xdata *)0xff23)	/* PWM2T2¼ÆÊýµÍ×Ö½Ú */
#define PWM2CR      (*(unsigned char volatile xdata *)0xff24)	/* PWM2¿ØÖÆ         */
#define PWM2HLD     (*(unsigned char volatile xdata *)0xff25)	/*          */

#define PWM3T1H     (*(unsigned char volatile xdata *)0xff30)	/* PWM3T1¼ÆÊý¸ß×Ö½Ú */
#define PWM3T1L     (*(unsigned char volatile xdata *)0xff31)	/* PWM3T1¼ÆÊýµÍ×Ö½Ú */
#define PWM3T2H     (*(unsigned char volatile xdata *)0xff32)	/* PWM3T2¼ÆÊý¸ß×Ö½Ú */
#define PWM3T2L     (*(unsigned char volatile xdata *)0xff33)	/* PWM3T2¼ÆÊýµÍ×Ö½Ú */
#define PWM3CR      (*(unsigned char volatile xdata *)0xff34)	/* PWM3¿ØÖÆ         */
#define PWM3HLD     (*(unsigned char volatile xdata *)0xff35)	/*          */

#define PWM4T1H     (*(unsigned char volatile xdata *)0xff40)	/* PWM4T1¼ÆÊý¸ß×Ö½Ú */
#define PWM4T1L     (*(unsigned char volatile xdata *)0xff41)	/* PWM4T1¼ÆÊýµÍ×Ö½Ú */
#define PWM4T2H     (*(unsigned char volatile xdata *)0xff42)	/* PWM4T2¼ÆÊý¸ß×Ö½Ú */
#define PWM4T2L     (*(unsigned char volatile xdata *)0xff43)	/* PWM4T2¼ÆÊýµÍ×Ö½Ú */
#define PWM4CR      (*(unsigned char volatile xdata *)0xff44)	/* PWM4¿ØÖÆ         */
#define PWM4HLD     (*(unsigned char volatile xdata *)0xff45)	/*          */

#define PWM5T1H     (*(unsigned char volatile xdata *)0xff50)	/* PWM5T1¼ÆÊý¸ß×Ö½Ú */
#define PWM5T1L     (*(unsigned char volatile xdata *)0xff51)	/* PWM5T1¼ÆÊýµÍ×Ö½Ú */
#define PWM5T2H     (*(unsigned char volatile xdata *)0xff52)	/* PWM5T2¼ÆÊý¸ß×Ö½Ú */
#define PWM5T2L     (*(unsigned char volatile xdata *)0xff53)	/* PWM5T2¼ÆÊýµÍ×Ö½Ú */
#define PWM5CR      (*(unsigned char volatile xdata *)0xff54)	/* PWM5¿ØÖÆ         */
#define PWM5HLD     (*(unsigned char volatile xdata *)0xff15)	/*          */

#define PWM6T1H     (*(unsigned char volatile xdata *)0xff60)	/* PWM6T1¼ÆÊý¸ß×Ö½Ú */
#define PWM6T1L     (*(unsigned char volatile xdata *)0xff61)	/* PWM6T1¼ÆÊýµÍ×Ö½Ú */
#define PWM6T2H     (*(unsigned char volatile xdata *)0xff62)	/* PWM6T2¼ÆÊý¸ß×Ö½Ú */
#define PWM6T2L     (*(unsigned char volatile xdata *)0xff63)	/* PWM6T2¼ÆÊýµÍ×Ö½Ú */
#define PWM6CR      (*(unsigned char volatile xdata *)0xff64)	/* PWM6¿ØÖÆ         */
#define PWM6HLD     (*(unsigned char volatile xdata *)0xff65)	/*          */

#define PWM7T1H     (*(unsigned char volatile xdata *)0xff70)	/* PWM7T1¼ÆÊý¸ß×Ö½Ú */        
#define PWM7T1L     (*(unsigned char volatile xdata *)0xff71)	/* PWM7T1¼ÆÊýµÍ×Ö½Ú */
#define PWM7T2H     (*(unsigned char volatile xdata *)0xff72)	/* PWM7T2¼ÆÊý¸ß×Ö½Ú */
#define PWM7T2L     (*(unsigned char volatile xdata *)0xff73)	/* PWM7T2¼ÆÊýµÍ×Ö½Ú */
#define PWM7CR      (*(unsigned char volatile xdata *)0xff74)	/* PWM7¿ØÖÆ         */
#define PWM7HLD     (*(unsigned char volatile xdata *)0xff75)	/*          */

#define PWMCH       (*(unsigned char volatile xdata *)0xfff0)	/* PWM¼ÆÊýÆ÷¸ß×Ö½Ú  */
#define PWMCL       (*(unsigned char volatile xdata *)0xfff1)	/* PWM¼ÆÊýÆ÷µÍ×Ö½Ú  */
#define PWMCKS      (*(unsigned char volatile xdata *)0xfff2)	/* PWMʱÖÓÑ¡Ôñ      */
#define TADCPH      (*(unsigned char volatile xdata *)0xfff3)	/* ÔÚ ETADC==1 µÄÇé¿öÏÂ,  ÿһ¸öÖÜÆÚÖÐ, µ±Counter¼ÆÊýµ½ TADCP[15:0] ʱ,×Ô¶¯Æô¶¯ ADC*/
#define TADCPL      (*(unsigned char volatile xdata *)0xfff4)	/* ´¥·¢ADCÑ¡ÔñµÍ×Ö½Ú*/


#define	PWM0_ID		0
#define	PWM1_ID		1
#define	PWM2_ID		2
#define	PWM3_ID		3
#define	PWM4_ID		4
#define	PWM5_ID		5
#define	PWM6_ID		6
#define	PWM7_ID		7

#define	PwmClk_T2	0

//                    7   6   5   4     3        2       1        0      Reset Value
//PWMnCR:  PWMn¿ØÖÆ   ENCnO   -   -   -   PWMn_PS  EPWMnI  ECnT2SI  ECnT1SI   0000,0000
#define	PWM_ENCnO		0x80	/* PWM¹Ü½ÅÑ¡Ôñλ */
#define	PWM_CnINI		0x40	/* PWM¹Ü½ÅÑ¡Ôñλ */
#define	PWMn_PS_0		0x00	/* PWM¹Ü½ÅÑ¡Ôñλ */
#define	PWMn_PS_1		0x08	/* PWM¹Ü½ÅÑ¡Ôñλ */
#define	PWMn_PS_2		0x10	/* PWM¹Ü½ÅÑ¡Ôñλ */
#define	PWM_ECnI		0x04	/* ÔÊÐíPWMÖÐ¶Ï   */
#define	PWM_ECnT2SI		0x02	/* ÔÊÐíT2·­×ªÊ±ÖÐ¶Ï */
#define	PWM_ECnT1SI		0x01	/* ÔÊÐíT1·­×ªÊ±ÖÐ¶Ï */

#define	PWM0_P20	0x00
#define	PWM0_P10	0x08
#define	PWM0_P60	0x10
#define	PWM1_P21	0x00
#define	PWM1_P11	0x08
#define	PWM1_P61	0x10
#define	PWM2_P22	0x00
#define	PWM2_P12	0x08
#define	PWM2_P62	0x10
#define	PWM3_P23	0x00
#define	PWM3_P13	0x08
#define	PWM3_P63	0x10
#define	PWM4_P24	0x00
#define	PWM4_P14	0x08
#define	PWM4_P64	0x10
#define	PWM5_P25	0x00
#define	PWM5_P15	0x08
#define	PWM5_P65	0x10
#define	PWM6_P26	0x00
#define	PWM6_P16	0x08
#define	PWM6_P66	0x10
#define	PWM7_P27	0x00
#define	PWM7_P17	0x08
#define	PWM7_P67	0x10

//                      7      6    5   4   3  2  1  0   Reset Value
//PWMCFG:  ÅäÖüĴæÆ÷  CBIF  ETADC  -   -   -  -  -  -    0000,0000
#define	CBIF	0x80	/* PWM¼ÆÊýÆ÷¹éÁãÖжϱê־λ */
#define	ETADC	0x40	/* PWMÓëADC¹ØÁª, ÓÉTADCPÉèÖô¥·¢Ê±¿Ì. */

//                        7     6     5     4     3     2     1     0     Reset Value
//PWMIF: ÖжϱêÖ¾¼Ä´æÆ÷  C7IF  C6IF  C5IF  C4IF  C3IF  C2IF  C1IF  C0IF    0000,0000
#define	C7IF	0x80
#define	C6IF	0x40	/* µÚnͨµÀµÄPWMÖжϱê־λ */
#define	C5IF	0x20
#define	C4IF	0x10
#define	C3IF	0x08
#define	C2IF	0x04
#define	C1IF	0x02
#define	C0IF	0x01

//                        7     6     5     4     3     2     1     0     Reset Value
//PWMFDCR: Òì³£¼ì²â¿ØÖƼĴæÆ÷  C7IF  C6IF  C5IF  C4IF  C3IF  C2IF  C1IF  C0IF    0000,0000
#define	INVCMP		0x80	/* 0: ±È½ÏÆ÷½á¹ûÓɵͱä¸ßΪÒì³£ÐźÅ, 1: ±È½ÏÆ÷½á¹ûÓɸ߱äµÍΪÒì³£ÐźŠ*/
#define	INVIO		0x40	/* 0: P3.5Óɵͱä¸ßΪÒì³£ÐźÅ, 1: P3.5Óɸ߱äµÍΪÒì³£ÐźÅ*/
#define	INVP35		0x40	/* 0: P3.5Óɵͱä¸ßΪÒì³£ÐźÅ, 1: P3.5Óɸ߱äµÍΪÒì³£ÐźÅ*/
#define	ENFD		0x20	/* 0: ¹Ø±ÕPWMÍⲿÒì³£¼ì²â¹¦, 1: ÔÊÐíPWMÍⲿÒì³£¼ì²â¹¦ */
#define	FLTFLIO		0x10	/* 0: ·¢ÉúWMÍⲿÒ쳣ʱ£¬PWMµÄÊä³ö¿Ú²»±ä,  1: ·¢ÉúWMÍⲿÒ쳣ʱ£¬PWMµÄÊä³ö¿ÚÁ¢¼´±»ÉèÖÃΪ¸ß×èÊäÈëģʽ¡££¨×¢£ºÖ»ÓÐENCnO==1Ëù¶ÔÓ¦µÄ¶Ë¿Ú²Å»á±»Ç¿ÖÆÐü¿Õ£© */
#define	EFDI		0x08	/* 1: ʹÄÜPWMÒì³£¼ì²âÖжÏ, 0: ¹Ø±ÕPWMÒì³£¼ì²âÖжÏ(FDIFÒÀÈ»»á±»Ó²¼þÖÃλ) */
#define	FDCMP		0x04	/* 1: É趨PWMÒì³£¼ì²âԴΪ±È½ÏÆ÷Êä³ö(Òì³£ÀàÐÍÓÉINVCMPÉ趨), 0: ±È½ÏÆ÷ÓëPWMÎÞ¹Ø */
#define	FDIO		0x02	/* 1: P3.5ÉèÖÃΪPWMÒì³£¼ì²â, Òì³£ÀàÐÍÓÉINVIOÉ趨, 0: P3.5ÓëPWMÎÞ¹Ø */
#define	FDIF		0x01	/* Òì³£Öжϱê־λ, µ±·¢ÉúPWMÒì³££¨±È½ÏÆ÷µÄÊä³öÓɵͱä¸ß»òÕßP3.5µÄµçƽÓɵͱä¸ß£©Ê±£¬Ó²¼þ×Ô¶¯½«´ËλÖÃ1, ²¢ÖÃλÖжϱêÖ¾.ÐèÒªÈí¼þÇåÁã */
#define	PWM_FaultDetect_Enable()	PWMFDCR |=  0x20		/* ʹÄÜPWMµÄÍⲿÒì³£¼ì²â¹¦ÄÜ */
#define	PWM_FaultDetect_Disable()	PWMFDCR &= ~0x20		/* ½ûÖ¹PWMµÄÍⲿÒì³£¼ì²â¹¦ÄÜ */

//                        7     6    5  4  3  2  1  0   Reset Value
//PWMCR: PWM¿ØÖƼĴæÆ÷  ENPWM  ECBI  -  -  -  -  -  -   0000,0000
#define	ENPWM	0x80	/* ʹÄÜPWM²¨Ðη¢ÉúÆ÷£¬PWM¼ÆÊýÆ÷¿ªÊ¼¼ÆÊý */
#define	ECBI	0x40	/* ʹÄÜPWM¼ÆÊýÆ÷¹éÁãÖÐ¶Ï */
#define	PWM_Enable()	PWMCR |=  0x80	/* ʹÄÜPWM²¨Ðη¢ÉúÆ÷£¬PWM¼ÆÊýÆ÷¿ªÊ¼¼ÆÊý */
#define	PWM_Disable()	PWMCR &= ~0x80	/* ¹Ø±ÕPWM²¨Ðη¢ÉúÆ÷ */



/*  BIT Registers  */
/*  PSW   */
sbit CY   = PSW^7;
sbit AC   = PSW^6;
sbit F0   = PSW^5;
sbit RS1  = PSW^4;
sbit RS0  = PSW^3;
sbit OV   = PSW^2;
sbit F1   = PSW^1;
sbit P    = PSW^0;

/*  TCON  */
sbit TF1  = TCON^7;	//¶¨Ê±Æ÷1Òç³öÖжϱê־λ
sbit TR1  = TCON^6;	//¶¨Ê±Æ÷1ÔËÐпØÖÆλ
sbit TF0  = TCON^5;	//¶¨Ê±Æ÷0Òç³öÖжϱê־λ
sbit TR0  = TCON^4;	//¶¨Ê±Æ÷0ÔËÐпØÖÆλ
sbit IE1  = TCON^3;	//ÍâÖжÏ1±ê־λ
sbit IT1  = TCON^2;	//ÍâÖжÏ1Ðźŷ½Ê½¿ØÖÆ룬1£ºÏ½µÑØÖжϣ¬0£ºÉÏÉýϽµ¾ùÖжϡ£
sbit IE0  = TCON^1;	//ÍâÖжÏ0±ê־λ
sbit IT0  = TCON^0;	//ÍâÖжÏ0Ðźŷ½Ê½¿ØÖÆ룬1£ºÏ½µÑØÖжϣ¬0£ºÉÏÉýϽµ¾ùÖжϡ£

/*  P0  */
sbit  P00 = P0^0;
sbit  P01 = P0^1;
sbit  P02 = P0^2;
sbit  P03 = P0^3;
sbit  P04 = P0^4;
sbit  P05 = P0^5;
sbit  P06 = P0^6;
sbit  P07 = P0^7;

/*  P1  */
sbit  P10 = P1^0;
sbit  P11 = P1^1;
sbit  P12 = P1^2;
sbit  P13 = P1^3;
sbit  P14 = P1^4;
sbit  P15 = P1^5;
sbit  P16 = P1^6;
sbit  P17 = P1^7;

sbit  RXD2      = P1^0;
sbit  TXD2      = P1^1;
sbit  CCP1      = P1^0;
sbit  CCP0      = P1^1;
sbit  SPI_SS    = P1^2;
sbit  SPI_MOSI  = P1^3;
sbit  SPI_MISO  = P1^4;
sbit  SPI_SCLK  = P1^5;

sbit  SPI_SS_2    = P2^4;
sbit  SPI_MOSI_2  = P2^3;
sbit  SPI_MISO_2  = P2^2;
sbit  SPI_SCLK_2  = P2^1;

sbit  SPI_SS_3    = P5^4;
sbit  SPI_MOSI_3  = P4^0;
sbit  SPI_MISO_3  = P4^1;
sbit  SPI_SCLK_3  = P4^3;

/*  P2  */
sbit  P20 = P2^0;
sbit  P21 = P2^1;
sbit  P22 = P2^2;
sbit  P23 = P2^3;
sbit  P24 = P2^4;
sbit  P25 = P2^5;
sbit  P26 = P2^6;
sbit  P27 = P2^7;

/*  P3  */
sbit  P30 = P3^0;
sbit  P31 = P3^1;
sbit  P32 = P3^2;
sbit  P33 = P3^3;
sbit  P34 = P3^4;
sbit  P35 = P3^5;
sbit  P36 = P3^6;
sbit  P37 = P3^7;

sbit RXD  = P3^0;
sbit TXD  = P3^1;
sbit INT0 = P3^2;
sbit INT1 = P3^3;
sbit T0   = P3^4;
sbit T1   = P3^5;
sbit WR   = P3^6;
sbit RD   = P3^7;
sbit CCP2  = P3^7;

sbit CLKOUT0   = P3^5;
sbit CLKOUT1   = P3^4;

/*  P4  */
sbit  P40 = P4^0;
sbit  P41 = P4^1;
sbit  P42 = P4^2;
sbit  P43 = P4^3;
sbit  P44 = P4^4;
sbit  P45 = P4^5;
sbit  P46 = P4^6;
sbit  P47 = P4^7;

/*  P5  */
sbit  P50 = P5^0;
sbit  P51 = P5^1;
sbit  P52 = P5^2;
sbit  P53 = P5^3;
sbit  P54 = P5^4;
sbit  P55 = P5^5;
sbit  P56 = P5^6;
sbit  P57 = P5^7;

/*  P6  */
sbit  P60 = P6^0;
sbit  P61 = P6^1;
sbit  P62 = P6^2;
sbit  P63 = P6^3;
sbit  P64 = P6^4;
sbit  P65 = P6^5;
sbit  P66 = P6^6;
sbit  P67 = P6^7;

/*  P7  */
sbit  P70 = P7^0;
sbit  P71 = P7^1;
sbit  P72 = P7^2;
sbit  P73 = P7^3;
sbit  P74 = P7^4;
sbit  P75 = P7^5;
sbit  P76 = P7^6;
sbit  P77 = P7^7;


/*  SCON  */
sbit SM0  = SCON^7;	//SM0/FE		SM0 SM1 = 00 ~ 11: ·½Ê½0~3
sbit SM1  = SCON^6;	//
sbit SM2  = SCON^5;	//¶à»úͨѶ
sbit REN  = SCON^4;	//½ÓÊÕÔÊÐí
sbit TB8  = SCON^3;	//·¢ËÍÊý¾ÝµÚ8λ
sbit RB8  = SCON^2;	//½ÓÊÕÊý¾ÝµÚ8λ
sbit TI   = SCON^1;	//·¢ËÍÖжϱê־λ
sbit RI   = SCON^0;	//½ÓÊÕÖжϱê־λ

/*  IE   */
sbit EA   = IE^7;	//ÖжÏÔÊÐí×Ü¿ØÖÆλ
sbit ELVD = IE^6;	//µÍѹ¼à²âÖжÏÔÊÐíλ
sbit EADC = IE^5;	//ADC ÖÐ¶Ï ÔÊÐíλ
sbit ES   = IE^4;	//´®ÐÐÖÐ¶Ï ÔÊÐí¿ØÖÆλ
sbit ET1  = IE^3;	//¶¨Ê±ÖжÏ1ÔÊÐí¿ØÖÆλ
sbit EX1  = IE^2;	//ÍⲿÖжÏ1ÔÊÐí¿ØÖÆλ
sbit ET0  = IE^1;	//¶¨Ê±ÖжÏ0ÔÊÐí¿ØÖÆλ
sbit EX0  = IE^0;	//ÍⲿÖжÏ0ÔÊÐí¿ØÖÆλ

sbit ACC0 = ACC^0;
sbit ACC1 = ACC^1;
sbit ACC2 = ACC^2;
sbit ACC3 = ACC^3;
sbit ACC4 = ACC^4;
sbit ACC5 = ACC^5;
sbit ACC6 = ACC^6;
sbit ACC7 = ACC^7;

sbit B0 = B^0;
sbit B1 = B^1;
sbit B2 = B^2;
sbit B3 = B^3;
sbit B4 = B^4;
sbit B5 = B^5;
sbit B6 = B^6;
sbit B7 = B^7;


//							7     6     5    4    3    2    1     0    Reset Value
//sfr IE2       = 0xAF;		-     -     -    -    -    -   ESPI  ES2   0000,0000B	//Auxiliary Interrupt   
#define		SPI_INT_ENABLE()		IE2 |=  2	/* ÔÊÐíSPIÖжÏ		*/
#define		SPI_INT_DISABLE()		IE2 &= ~2	/* ÔÊÐíSPIÖжÏ		*/
#define		UART2_INT_ENABLE()		IE2 |=  1	/* ÔÊÐí´®¿Ú2ÖжÏ	*/
#define		UART2_INT_DISABLE()		IE2 &= ~1	/* ÔÊÐí´®¿Ú2ÖжÏ	*/

//                                          7     6     5    4    3    2    1    0    Reset Value
//sfr IP      = 0xB8; //ÖжÏÓÅÏȼ¶µÍλ      PPCA  PLVD  PADC  PS   PT1  PX1  PT0  PX0   0000,0000
//--------
sbit PPCA	= IP^7;	//PCA Ä£¿éÖжÏÓÅÏȼ¶
sbit PLVD	= IP^6;	//µÍѹ¼à²âÖжÏÓÅÏȼ¶
sbit PADC	= IP^5;	//ADC ÖжÏÓÅÏȼ¶
sbit PS   	= IP^4;	//´®ÐÐÖжÏ0ÓÅÏȼ¶É趨λ
sbit PT1	= IP^3;	//¶¨Ê±ÖжÏ1ÓÅÏȼ¶É趨λ
sbit PX1	= IP^2;	//ÍⲿÖжÏ1ÓÅÏȼ¶É趨λ
sbit PT0	= IP^1;	//¶¨Ê±ÖжÏ0ÓÅÏȼ¶É趨λ
sbit PX0	= IP^0;	//ÍⲿÖжÏ0ÓÅÏȼ¶É趨λ

//                                           7      6      5     4     3     2    1     0        Reset Value
//sfr IPH   = 0xB7; //ÖжÏÓÅÏȼ¶¸ßλ       PPCAH  PLVDH  PADCH  PSH  PT1H  PX1H  PT0H  PX0H   0000,0000
//sfr IP2   = 0xB5; //                       -      -      -     -     -     -   PSPI   PS2   xxxx,xx00
//sfr IP2H  = 0xB6; //                       -      -      -     -     -     -   PSPIH  PS2H  xxxx,xx00
#define		PPCAH	0x80
#define		PLVDH	0x40
#define		PADCH	0x20
#define		PSH		0x10
#define		PT1H	0x08
#define		PX1H	0x04
#define		PT0H	0x02
#define		PX0H	0x01

#define		PCA_InterruptFirst()	PPCA = 1
#define		LVD_InterruptFirst()	PLVD = 1
#define		ADC_InterruptFirst()	PADC = 1
#define		UART1_InterruptFirst()	PS   = 1
#define		Timer1_InterruptFirst()	PT1  = 1
#define		INT1_InterruptFirst()	PX1  = 1
#define		Timer0_InterruptFirst()	PT0  = 1
#define		INT0_InterruptFirst()	PX0  = 1


/*************************************************************************************************/


//                       7      6     5    4    3    2     1      0        Reset Value
//sfr CMPCR1 = 0xE6;   CMPEN  CMPIF  PIE  NIE  PIS  NIS  CMPOE  CMPRES      00000000B
#define	CMPEN	0x80	//1: ÔÊÐí±È½ÏÆ÷, 0: ½ûÖ¹,¹Ø±Õ±È½ÏÆ÷µçÔ´
#define	CMPIF	0x40	//±È½ÏÆ÷ÖжϱêÖ¾, °üÀ¨ÉÏÉýÑØ»òϽµÑØÖжÏ, Èí¼þÇå0
#define	PIE		0x20	//1: ±È½Ï½á¹ûÓÉ0±ä1, ²úÉúÉÏÉýÑØÖжÏ
#define	NIE		0x10	//1: ±È½Ï½á¹ûÓÉ1±ä0, ²úÉúϽµÑØÖжÏ
#define	PIS		0x08	//ÊäÈëÕý¼«ÐÔÑ¡Ôñ, 0: Ñ¡ÔñÄÚ²¿P5.5×öÕýÊäÈë,           1: ÓÉADCIS[2:0]ËùÑ¡ÔñµÄADCÊäÈë¶Ë×öÕýÊäÈë.
#define	NIS		0x04	//ÊäÈ븺¼«ÐÔÑ¡Ôñ, 0: Ñ¡ÔñÄÚ²¿BandGapµçѹBGv×ö¸ºÊäÈë, 1: Ñ¡ÔñÍⲿP5.4×öÊäÈë.
#define	CMPOE	0x02	//1: ÔÊÐí±È½Ï½á¹ûÊä³öµ½P1.2, 0: ½ûÖ¹.
#define	CMPRES	0x01	//±È½Ï½á¹û, 1: CMP+µçƽ¸ßÓÚCMP-,  0: CMP+µçƽµÍÓÚCMP-,  Ö»¶Á

//                       7        6       5  4  3  2  1  0    Reset Value
//sfr CMPCR2 = 0xE7;   INVCMPO  DISFLT       LCDTY[5:0]       00001001B
#define	INVCMPO	0x80	//1: ±È½ÏÆ÷Êä³öÈ¡·´,  0: ²»È¡·´
#define	DISFLT	0x40	//1: ¹Ø±Õ0.1uFÂ˲¨,   0: ÔÊÐí
#define	LCDTY	0x00	//0~63, ±È½Ï½á¹û±ä»¯ÑÓʱÖÜÆÚÊý


/*************************************************************************************************/
//                     7     6     5    4    3    2   1   0       Reset Value
//sfr SCON  = 0x98;   SM0   SM1   SM2  REN  TB8  RB8  TI  RI      00000000B		 //S1 Control

#define		S1_DoubleRate()		PCON  |=  0x80
#define		S1_SHIFT()			SCON  &=  0x3f

#define		S1_8bit()			SCON   =  (SCON & 0x3f) | 0x40
#define		S1_9bit()			SCON   =  (SCON & 0x3f) | 0xc0
#define		S1_RX_Enable()		SCON  |=  0x10
#define		S1_RX_Disable()		SCON  &= ~0x10
#define		TI1					TI					/* ÅжÏTI1ÊÇ·ñ·¢ËÍÍê³É								 */
#define		RI1					RI					/* ÅжÏRI1ÊÇ·ñ½ÓÊÕÍê³É								 */
#define		SET_TI1()			TI = 1				/* ÉèÖÃTI1(ÒýÆðÖжÏ)								 */
#define		CLR_TI1()			TI = 0				/* Çå³ýTI1											 */
#define		CLR_RI1()			RI = 0				/* Çå³ýRI1											 */
#define		S1TB8_SET()			TB8 = 1				/* ÉèÖÃTB8											 */
#define		S1TB8_CLR()			TB8 = 0				/* Çå³ýTB8											 */
#define		S1_Int_Enable()		ES     =  1			/* ´®¿Ú1ÔÊÐíÖжÏ									 */
#define		S1_Int_Disable()	ES     =  0			/* ´®¿Ú1½ûÖ¹ÖжÏ									 */
#define 	S1_BRT_UseTimer1()	AUXR  &= ~1
#define 	S1_BRT_UseTimer2()	AUXR  |=  1
#define		S1_USE_P30P31()		P_SW1 &= ~0xc0						//UART1 ʹÓÃP30 P31¿Ú	ĬÈÏ
#define		S1_USE_P36P37()		P_SW1  =  (P_SW1 & ~0xc0) | 0x40	//UART1 ʹÓÃP36 P37¿Ú
#define		S1_USE_P16P17()		P_SW1  =  (P_SW1 & ~0xc0) | 0x80	//UART1 ʹÓÃP16 P17¿Ú
#define		S1_TXD_RXD_SHORT()	PCON2 |=  (1<<4)	//½«TXDÓëRXDÁ¬½ÓÖмÌÊä³ö
#define		S1_TXD_RXD_OPEN()	PCON2 &= ~(1<<4)	//½«TXDÓëRXDÁ¬½ÓÖм̶Ͽª	ĬÈÏ

//						  7      6      5      4      3      2     1     0        Reset Value
//sfr S2CON = 0x9A;		S2SM0    -    S2SM2  S2REN  S2TB8  S2RB8  S2TI  S2RI      00000000B		 //S2 Control

#define		S2_MODE0()			S2CON &= ~(1<<7)	/* ´®¿Ú2ģʽ0£¬8λUART£¬²¨ÌØÂÊ = ¶¨Ê±Æ÷2µÄÒç³öÂÊ / 4 */
#define		S2_MODE1()			S2CON |=  (1<<7)	/* ´®¿Ú2ģʽ1£¬9λUART£¬²¨ÌØÂÊ = ¶¨Ê±Æ÷2µÄÒç³öÂÊ / 4 */
#define		S2_8bit()			S2CON &= ~(1<<7)	/* ´®¿Ú2ģʽ0£¬8λUART£¬²¨ÌØÂÊ = ¶¨Ê±Æ÷2µÄÒç³öÂÊ / 4 */
#define		S2_9bit()			S2CON |=  (1<<7)	/* ´®¿Ú2ģʽ1£¬9λUART£¬²¨ÌØÂÊ = ¶¨Ê±Æ÷2µÄÒç³öÂÊ / 4 */
#define		S2_RX_Enable()		S2CON |=  (1<<4)	/* ÔÊÐí´®2½ÓÊÕ										 */
#define		S2_RX_Disable()		S2CON &= ~(1<<4)	/* ½ûÖ¹´®2½ÓÊÕ										 */
#define		TI2					(S2CON & 2) != 0	/* ÅжÏTI2ÊÇ·ñ·¢ËÍÍê³É								 */
#define		RI2					(S2CON & 1) != 0	/* ÅжÏRI2ÊÇ·ñ½ÓÊÕÍê³É								 */
#define		SET_TI2()			S2CON |=  (1<<1)	/* ÉèÖÃTI2(ÒýÆðÖжÏ)								 */
#define		CLR_TI2()			S2CON &= ~(1<<1)	/* Çå³ýTI2											 */
#define		CLR_RI2()			S2CON &= ~1			/* Çå³ýRI2											 */
#define		S2TB8_SET()			S2CON |=  (1<<3)	/* ÉèÖÃTB8											 */
#define		S2TB8_CLR()			S2CON &= ~(1<<3)	/* Çå³ýTB8											 */
#define		S2_Int_Enable()		IE2   |=  1			/* ´®¿Ú2ÔÊÐíÖжÏ									 */
#define		S2_Int_Disable()	IE2   &= ~1			/* ´®¿Ú2½ûÖ¹ÖжÏ									 */
#define		S2_USE_P10P11()		P_SW2 &= ~1			/* UART2 ʹÓÃP1¿Ú	ĬÈÏ							 */
#define		S2_USE_P46P47()		P_SW2 |=  1			/* UART2 ʹÓÃP4¿Ú									 */

//						  7      6      5      4      3      2     1     0        Reset Value
//sfr S3CON = 0xAC;		S3SM0  S3ST3  S3SM2  S3REN  S3TB8  S3RB8  S3TI  S3RI      00000000B		 //S3 Control

#define		S3_MODE0()			S3CON &= ~(1<<7)	/* ´®¿Ú3ģʽ0£¬8λUART£¬²¨ÌØÂÊ = ¶¨Ê±Æ÷µÄÒç³öÂÊ / 4  */
#define		S3_MODE1()			S3CON |=  (1<<7)	/* ´®¿Ú3ģʽ1£¬9λUART£¬²¨ÌØÂÊ = ¶¨Ê±Æ÷µÄÒç³öÂÊ / 4  */
#define		S3_8bit()			S3CON &= ~(1<<7)	/* ´®¿Ú3ģʽ0£¬8λUART£¬²¨ÌØÂÊ = ¶¨Ê±Æ÷µÄÒç³öÂÊ / 4  */
#define		S3_9bit()			S3CON |=  (1<<7)	/* ´®¿Ú3ģʽ1£¬9λUART£¬²¨ÌØÂÊ = ¶¨Ê±Æ÷µÄÒç³öÂÊ / 4  */
#define		S3_RX_Enable()		S3CON |=  (1<<4)	/* ÔÊÐí´®3½ÓÊÕ									     */
#define		S3_RX_Disable()		S3CON &= ~(1<<4)	/* ½ûÖ¹´®3½ÓÊÕ									     */
#define		TI3					(S3CON & 2) != 0	/* ÅжÏTI3ÊÇ·ñ·¢ËÍÍê³É								 */
#define		RI3					(S3CON & 1) != 0	/* ÅжÏRI3ÊÇ·ñ½ÓÊÕÍê³É								 */
#define		SET_TI3()			S3CON |=  (1<<1)	/* ÉèÖÃTI3(ÒýÆðÖжÏ)								 */
#define		CLR_TI3()			S3CON &= ~(1<<1)	/* Çå³ýTI3											 */
#define		CLR_RI3()			S3CON &= ~1			/* Çå³ýRI3											 */
#define		S3TB8_SET()			S3CON |=  (1<<3)	/* ÉèÖÃTB8											 */
#define		S3TB8_CLR()			S3CON &= ~(1<<3)	/* Çå³ýTB8											 */
#define		S3_Int_Enable()		IE2   |=  (1<<3)	/* ´®¿Ú3ÔÊÐíÖжÏ								     */
#define		S3_Int_Disable()	IE2   &= ~(1<<3)	/* ´®¿Ú3½ûÖ¹ÖжÏ								     */
#define 	S3_BRT_UseTimer3()	S3CON |=  (1<<6)	/* BRT select Timer3								 */
#define 	S3_BRT_UseTimer2()	S3CON &= ~(1<<6)	/* BRT select Timer2								 */
#define		S3_USE_P00P01()		P_SW2 &= ~2			/* UART3 ʹÓÃP0¿Ú	ĬÈÏ						     */
#define		S3_USE_P50P51()		P_SW2 |=  2			/* UART3 ʹÓÃP5¿Ú								     */

//						  7      6      5      4      3      2     1     0        Reset Value
//sfr S4CON = 0x84;		S4SM0  S4ST4  S4SM2  S4REN  S4TB8  S4RB8  S4TI  S4RI      00000000B		 //S4 Control

#define		S4_MODE0()			S4CON &= ~(1<<7)	/* ´®¿Ú4ģʽ0£¬8λUART£¬²¨ÌØÂÊ = ¶¨Ê±Æ÷µÄÒç³öÂÊ / 4  */
#define		S4_MODE1()			S4CON |=  (1<<7)	/* ´®¿Ú4ģʽ1£¬9λUART£¬²¨ÌØÂÊ = ¶¨Ê±Æ÷µÄÒç³öÂÊ / 4  */
#define		S4_8bit()			S4CON &= ~(1<<7)	/* ´®¿Ú4ģʽ0£¬8λUART£¬²¨ÌØÂÊ = ¶¨Ê±Æ÷µÄÒç³öÂÊ / 4  */
#define		S4_9bit()			S4CON |=  (1<<7)	/* ´®¿Ú4ģʽ1£¬9λUART£¬²¨ÌØÂÊ = ¶¨Ê±Æ÷µÄÒç³öÂÊ / 4  */
#define		S4_RX_Enable()		S4CON |=  (1<<4)	/* ÔÊÐí´®4½ÓÊÕ									     */
#define		S4_RX_Disable()		S4CON &= ~(1<<4)	/* ½ûÖ¹´®4½ÓÊÕ									     */
#define		TI4					(S4CON & 2) != 0	/* ÅжÏTI3ÊÇ·ñ·¢ËÍÍê³É							     */
#define		RI4					(S4CON & 1) != 0	/* ÅжÏRI3ÊÇ·ñ½ÓÊÕÍê³É							     */
#define		SET_TI4()			S4CON |=  2			/* ÉèÖÃTI3(ÒýÆðÖжÏ)							     */
#define		CLR_TI4()			S4CON &= ~2			/* Çå³ýTI3										     */
#define		CLR_RI4()			S4CON &= ~1			/* Çå³ýRI3										     */
#define		S4TB8_SET()			S4CON |=  8			/* ÉèÖÃTB8										     */
#define		S4TB8_CLR()			S4CON &= ~8			/* Çå³ýTB8										     */
#define		S4_Int_Enable()		IE2   |=  (1<<4)	/* ´®¿Ú4ÔÊÐíÖжÏ								     */
#define		S4_Int_Disable()	IE2   &= ~(1<<4)	/* ´®¿Ú4½ûÖ¹ÖжÏ								     */
#define 	S4_BRT_UseTimer4()	S4CON |=  (1<<6)	/* BRT select Timer4								 */
#define 	S4_BRT_UseTimer2()	S4CON &= ~(1<<6)	/* BRT select Timer2								 */
#define		S4_USE_P02P03()		P_SW2 &= ~4			/* UART4 ʹÓÃP0¿Ú	ĬÈÏ						     */
#define		S4_USE_P52P53()		P_SW2 |=  4			/* UART4 ʹÓÃP5¿Ú								     */




/**********************************************************/
//						   7     6       5      4     3      2      1      0    Reset Value
//sfr AUXR  = 0x8E;		T0x12 T1x12 UART_M0x6  T2R  T2_C/T T2x12 EXTRAM  S1ST2  0000,0000	//Auxiliary Register 

#define 	ExternalRAM_enable()		AUXR |=  2		/* ÔÊÐíÍⲿXRAM£¬½ûֹʹÓÃÄÚ²¿1024RAM     */
#define 	InternalRAM_enable()		AUXR &= ~2		/* ½ûÖ¹ÍⲿXRAM£¬ÔÊÐíʹÓÃÄÚ²¿1024RAM     */
#define		S1_M0x6()					AUXR |=  (1<<5)	/* UART Mode0 Speed is 6x Standard       */
#define		S1_M0x1()					AUXR &= ~(1<<5)	/* default,	UART Mode0 Speed is Standard */

//====================================
#define		Timer0_16bitAutoReload()	TMOD &= ~0x03					/* 16λ×Ô¶¯ÖØ×°	*/
#define		Timer0_16bit()				TMOD  = (TMOD & ~0x03) | 0x01	/* 16λ         */
#define		Timer0_8bitAutoReload()		TMOD  = (TMOD & ~0x03) | 0x02	/* 8λ×Ô¶¯ÖØ×°	*/
#define		Timer0_16bitAutoRL_NoMask()	TMOD |=  0x03		/* 16λ×Ô¶¯ÖØ×°²»¿ÉÆÁ±ÎÖжÏ	*/
#define 	Timer0_Run()	 			TR0 = 1				/* ÔÊÐí¶¨Ê±Æ÷0¼ÆÊý			*/
#define 	Timer0_Stop()	 			TR0 = 0				/* ½ûÖ¹¶¨Ê±Æ÷0¼ÆÊý			*/
#define		Timer0_Gate_INT0_P32()		TMOD |=  (1<<3)		/* ʱÆ÷0ÓÉÍⲿINT0¸ßµçƽÔÊÐí¶¨Ê±¼ÆÊý */
#define		Timer0_AsTimer()			TMOD &= ~(1<<2)		/* ʱÆ÷0ÓÃ×ö¶¨Ê±Æ÷	*/
#define		Timer0_AsCounter()			TMOD |=  (1<<2)		/* ʱÆ÷0ÓÃ×ö¼ÆÊýÆ÷	*/
#define		Timer0_AsCounterP34()		TMOD |=  (1<<2)		/* ʱÆ÷0ÓÃ×ö¼ÆÊýÆ÷	*/
#define 	Timer0_1T()					AUXR |=  (1<<7)		/* Timer0 clodk = fo	*/
#define 	Timer0_12T()				AUXR &= ~(1<<7)		/* Timer0 clodk = fo/12	12·ÖƵ,	default	*/
#define		Timer0_CLKO_Enable()		INT_CLKO |=  1			/* ÔÊÐí T0 Òç³öÂö³åÔÚT0(P3.5)½ÅÊä³ö£¬Fck0 = 1/2 T0 Òç³öÂÊ£¬T0¿ÉÒÔ1T»ò12T¡£	*/
#define		Timer0_CLKO_Disable()		INT_CLKO &= ~1
#define		Timer0_CLKO_Enable_P34()	INT_CLKO |=  1			/* ÔÊÐí T0 Òç³öÂö³åÔÚT0(P3.5)½ÅÊä³ö£¬Fck0 = 1/2 T0 Òç³öÂÊ£¬T0¿ÉÒÔ1T»ò12T¡£	*/
#define		Timer0_CLKO_Disable_P34()	INT_CLKO &= ~1
#define 	Timer0_InterruptEnable()	ET0 = 1				/* ÔÊÐíTimer1ÖжÏ.*/
#define 	Timer0_InterruptDisable()	ET0 = 0				/* ½ûÖ¹Timer1ÖжÏ.*/

#define		T0_Load(n)					TH0 = (n) / 256,	TL0 = (n) % 256
#define		T0_Load_us_1T(n)			Timer0_AsTimer(),Timer0_1T(), Timer0_16bitAutoReload(),TH0=(65536-((MAIN_Fosc/1000)*(n)+500)/1000)/256, TL0=(65536-((MAIN_Fosc/1000)*(n)+500)/1000)%256
#define		T0_Load_us_12T(n)			Timer0_AsTimer(),Timer0_12T(),Timer0_16bitAutoReload(),TH0=(65536-((MAIN_Fosc/12000)*(n)+500)/1000)/256,TL0=(65536-((MAIN_Fosc/12000)*(n)+500)/1000)%256
#define		T0_Frequency_1T_P35(n)		ET0=0,Timer0_AsTimer(),Timer0_1T(),Timer0_16bitAutoReload(),TH0=(65536-(n/2+MAIN_Fosc/2)/(n))/256,TL0=(65536-(n/2+MAIN_Fosc/2)/(n))%256,INT_CLKO |= bit0,TR0=1		/* fx=fosc/(2*M)/n,  M=1 or M=12 */
#define		T0_Frequency_12T_P35(n)		ET0=0,Timer0_AsTimer(),Timer0_12T(),Timer0_16bitAutoReload(),TH0=(65536-(n/2+MAIN_Fosc/24)/(n))/256,TL0=(65536-(n/2+MAIN_Fosc/24)/(n))%256,INT_CLKO |= bit0,TR0=1	/* fx=fosc/(2*M)/n,  M=1 or M=12 */

//====================================
#define		Timer1_16bitAutoReload()	TMOD &= ~0x30					/* 16λ×Ô¶¯ÖØ×°	*/
#define		Timer1_16bit()				TMOD  = (TMOD & ~0x30) | 0x10	/* 16λ			*/
#define		Timer1_8bitAutoReload()		TMOD  = (TMOD & ~0x30) | 0x20	/* 8λ×Ô¶¯ÖØ×°	*/
#define 	Timer1_Run()	 			TR1 = 1				/* ÔÊÐí¶¨Ê±Æ÷1¼ÆÊý			*/
#define 	Timer1_Stop()	 			TR1 = 0				/* ½ûÖ¹¶¨Ê±Æ÷1¼ÆÊý			*/
#define		Timer1_Gate_INT1_P33()		TMOD |=  (1<<7)		/* ʱÆ÷1ÓÉÍⲿINT1¸ßµçƽÔÊÐí¶¨Ê±¼ÆÊý	*/
#define		Timer1_AsTimer()			TMOD &= ~(1<<6)		/* ʱÆ÷1ÓÃ×ö¶¨Ê±Æ÷			*/
#define		Timer1_AsCounter()			TMOD |=  (1<<6)		/* ʱÆ÷1ÓÃ×ö¼ÆÊýÆ÷			*/
#define		Timer1_AsCounterP35()		TMOD |=  (1<<6)		/* ʱÆ÷1ÓÃ×ö¼ÆÊýÆ÷			*/
#define 	Timer1_1T()					AUXR |=  (1<<6)		/* Timer1 clodk = fo		*/
#define 	Timer1_12T()				AUXR &= ~(1<<6)		/* Timer1 clodk = fo/12	12·ÖƵ,	default	*/
#define		Timer1_CLKO_Enable()		INT_CLKO |=  2			/* ÔÊÐí T1 Òç³öÂö³åÔÚT1(P3.4)½ÅÊä³ö£¬Fck1 = 1/2 T1 Òç³öÂÊ£¬T1¿ÉÒÔ1T»ò12T¡£	*/
#define		Timer1_CLKO_Disable()		INT_CLKO &= ~2
#define		Timer1_CLKO_Enable_P35()	INT_CLKO |=  2			/* ÔÊÐí T1 Òç³öÂö³åÔÚT1(P3.4)½ÅÊä³ö£¬Fck1 = 1/2 T1 Òç³öÂÊ£¬T1¿ÉÒÔ1T»ò12T¡£	*/
#define		Timer1_CLKO_Disable_P35()	INT_CLKO &= ~2
#define 	Timer1_InterruptEnable()	ET1 = 1				/* ÔÊÐíTimer1ÖжÏ.	*/
#define 	Timer1_InterruptDisable()	ET1 = 0				/* ½ûÖ¹Timer1ÖжÏ.	*/

#define		T1_Load(n)					TH1 = (n) / 256,	TL1 = (n) % 256
#define		T1_Load_us_1T(n)			Timer1_AsTimer(),Timer1_1T(), Timer1_16bitAutoReload(),TH1=(65536-((MAIN_Fosc/1000)*(n)+500)/1000)/256, TL1=(65536-((MAIN_Fosc/1000)*(n)+500)/1000)%256
#define		T1_Load_us_12T(n)			Timer1_AsTimer(),Timer1_12T(),Timer1_16bitAutoReload(),TH1=(65536-((MAIN_Fosc/12000)*(n)+500)/1000)/256,TL1=(65536-((MAIN_Fosc/12000)*(n)+500)/1000)%256
#define		T1_Frequency_1T_P34(n)		ET1=0,Timer1_AsTimer(),Timer1_1T(),Timer1_16bitAutoReload(),TH1=(65536-(n/2+MAIN_Fosc/2)/(n))/256,TL1=(65536-(n/2+MAIN_Fosc/2)/(n))%256,INT_CLKO |= bit1,TR1=1		/* fx=fosc/(2*M)/n,  M=1 or M=12 */
#define		T1_Frequency_12T_P34(n)		ET1=0,Timer1_AsTimer(),Timer1_12T(),Timer1_16bitAutoReload(),TH1=(65536-(n/2+MAIN_Fosc/24)/(n))/256,TL1=(65536-(n/2+MAIN_Fosc/24)/(n))%256,INT_CLKO |= bit1,TR1=1	/* fx=fosc/(2*M)/n,  M=1 or M=12 */

//====================================
#define 	Timer2_Run()	 			AUXR |=  (1<<4)	/* ÔÊÐí¶¨Ê±Æ÷2¼ÆÊý	*/
#define 	Timer2_Stop()	 			AUXR &= ~(1<<4)	/* ½ûÖ¹¶¨Ê±Æ÷2¼ÆÊý	*/
#define		Timer2_AsTimer()			AUXR &= ~(1<<3)	/* ʱÆ÷2ÓÃ×ö¶¨Ê±Æ÷	*/
#define		Timer2_AsCounter()			AUXR |=  (1<<3)	/* ʱÆ÷2ÓÃ×ö¼ÆÊýÆ÷	*/
#define		Timer2_AsCounterP31()		AUXR |=  (1<<3)	/* ʱÆ÷2ÓÃ×ö¼ÆÊýÆ÷	*/
#define 	Timer2_1T()					AUXR |=  (1<<2)	/* Timer0 clock = fo	*/
#define 	Timer2_12T()				AUXR &= ~(1<<2)	/* Timer0 clock = fo/12	12·ÖƵ,	default	*/
#define		Timer2_CLKO_Enable()		INT_CLKO |=  4		/* ÔÊÐí T2 Òç³öÂö³åÔÚT1(P3.0)½ÅÊä³ö£¬Fck2 = 1/2 T2 Òç³öÂÊ£¬T2¿ÉÒÔ1T»ò12T¡£	*/
#define		Timer2_CLKO_Disable()		INT_CLKO &= ~4
#define		Timer2_CLKO_Enable_P30()	INT_CLKO |=  4		/* ÔÊÐí T2 Òç³öÂö³åÔÚT1(P3.0)½ÅÊä³ö£¬Fck2 = 1/2 T2 Òç³öÂÊ£¬T2¿ÉÒÔ1T»ò12T¡£	*/
#define		Timer2_CLKO_Disable_P30()	INT_CLKO &= ~4
#define 	Timer2_InterruptEnable()	IE2  |=  (1<<2)	/* ÔÊÐíTimer2ÖжÏ.	*/
#define 	Timer2_InterruptDisable()	IE2  &= ~(1<<2)	/* ½ûÖ¹Timer2ÖжÏ.	*/

#define		T2_Load(n)					TH2 = (n) / 256,	TL2 = (n) % 256
#define		T2_Load_us_1T(n)			Timer2_AsTimer(),Timer2_1T(), TH2=(65536-((MAIN_Fosc/1000)*(n)+500)/1000)/256, TL2=(65536-((MAIN_Fosc/1000)*(n)+500)/1000)%256
#define		T2_Load_us_12T(n)			Timer2_AsTimer(),Timer2_12T(),TH2=(65536-((MAIN_Fosc/12000)*(n)+500)/1000)/256,TL2=(65536-((MAIN_Fosc/12000)*(n)+500)/1000)%256
#define		T2_Frequency_1T_P30(n)		Timer2_InterruptDisable(),Timer2_AsTimer(),Timer2_1T(), TH2=(65536-(n/2+MAIN_Fosc/2)/(n))/256, TL2=(65536-(n/2+MAIN_Fosc/2)/(n))%256, Timer2_CLKO_Enable_P30(),Timer2_Run()	/* fx=fosc/(2*M)/n,  M=1 or M=12 */
#define		T2_Frequency_12T_P30(n)		Timer2_InterruptDisable(),Timer2_AsTimer(),Timer2_12T(),TH2=(65536-(n/2+MAIN_Fosc/24)/(n))/256,TL2=(65536-(n/2+MAIN_Fosc/24)/(n))%256,Timer2_CLKO_Enable_P30(),Timer2_Run()	/* fx=fosc/(2*M)/n,  M=1 or M=12 */

//====================================
#define 	Timer3_Run()	 			T4T3M |=  (1<<3)	/* ÔÊÐí¶¨Ê±Æ÷3¼ÆÊý	*/
#define 	Timer3_Stop()	 			T4T3M &= ~(1<<3)	/* ½ûÖ¹¶¨Ê±Æ÷3¼ÆÊý	*/
#define		Timer3_AsTimer()			T4T3M &= ~(1<<2)	/* ʱÆ÷3ÓÃ×ö¶¨Ê±Æ÷	*/
#define		Timer3_AsCounter()			T4T3M |=  (1<<2)	/* ʱÆ÷3ÓÃ×ö¼ÆÊýÆ÷, P0.5ΪÍⲿÂö³å	*/
#define		Timer3_AsCounterP05()		T4T3M |=  (1<<2)	/* ʱÆ÷3ÓÃ×ö¼ÆÊýÆ÷, P0.5ΪÍⲿÂö³å	*/
#define 	Timer3_1T()					T4T3M |=  (1<<1)	/* 1Tģʽ	*/
#define 	Timer3_12T()				T4T3M &= ~(1<<1)	/* 12Tģʽ,	default	*/
#define		Timer3_CLKO_Enable()		T4T3M |=  1			/* ÔÊÐíT3Òç³öÂö³åÔÚT3(P0.4)½ÅÊä³ö£¬Fck = 1/2 T2 Òç³öÂÊ£¬T2¿ÉÒÔ1T»ò12T¡£	*/
#define		Timer3_CLKO_Disable()		T4T3M &= ~1			/* ½ûÖ¹T3Òç³öÂö³åÔÚT3(P0.4)½ÅÊä³ö	*/
#define		Timer3_CLKO_Enable_P04()	T4T3M |=  1			/* ÔÊÐíT3Òç³öÂö³åÔÚT3(P0.4)½ÅÊä³ö£¬Fck = 1/2 T2 Òç³öÂÊ£¬T2¿ÉÒÔ1T»ò12T¡£	*/
#define		Timer3_CLKO_Disable_P04()	T4T3M &= ~1			/* ½ûÖ¹T3Òç³öÂö³åÔÚT3(P0.4)½ÅÊä³ö	*/
#define 	Timer3_InterruptEnable()	IE2  |=  (1<<5)		/* ÔÊÐíTimer3ÖжÏ.	*/
#define 	Timer3_InterruptDisable()	IE2  &= ~(1<<5)		/* ½ûÖ¹Timer3ÖжÏ.	*/

#define		T3_Load(n)					TH3 = (n) / 256,	TL3 = (n) % 256
#define		T3_Load_us_1T(n)			Timer3_AsTimer(),Timer3_1T(), TH3=(65536-((MAIN_Fosc/1000)*(n)+500)/1000)/256, TL3=(65536-((MAIN_Fosc/1000)*(n)+500)/1000)%256
#define		T3_Load_us_12T(n)			Timer3_AsTimer(),Timer3_12T(),TH3=(65536-((MAIN_Fosc/12000)*(n)+500)/1000)/256,TL3=(65536-((MAIN_Fosc/12000)*(n)+500)/1000)%256
#define		T3_Frequency_1T_P04(n)		Timer3_InterruptDisable(),Timer3_AsTimer(),Timer3_1T(), TH3=(65536-(n/2+MAIN_Fosc/2)/(n))/256, TL3=(65536-(n/2+MAIN_Fosc/2)/(n))%256, Timer3_CLKO_P04_Enable,Timer3_Run()	/* fx=fosc/(2*M)/n,  M=1 or M=12 */
#define		T3_Frequency_12T_P04(n)		Timer3_InterruptDisable(),Timer3_AsTimer(),Timer3_12T(),TH3=(65536-(n/2+MAIN_Fosc/24)/(n))/256,TL3=(65536-(n/2+MAIN_Fosc/24)/(n))%256,Timer3_CLKO_P04_Enable,Timer3_Run()	/* fx=fosc/(2*M)/n,  M=1 or M=12 */

//====================================
#define 	Timer4_Run()	 			T4T3M |=  (1<<7)	/* ÔÊÐí¶¨Ê±Æ÷4¼ÆÊý	*/
#define 	Timer4_Stop()	 			T4T3M &= ~(1<<7)	/* ½ûÖ¹¶¨Ê±Æ÷4¼ÆÊý	*/
#define		Timer4_AsTimer()			T4T3M &= ~(1<<6)	/* ʱÆ÷4ÓÃ×ö¶¨Ê±Æ÷  */
#define		Timer4_AsCounter()			T4T3M |=  (1<<6)	/* ʱÆ÷4ÓÃ×ö¼ÆÊýÆ÷, P0.7ΪÍⲿÂö³å	*/
#define		Timer4_AsCounterP07()		T4T3M |=  (1<<6)	/* ʱÆ÷4ÓÃ×ö¼ÆÊýÆ÷, P0.7ΪÍⲿÂö³å	*/
#define 	Timer4_1T()					T4T3M |=  (1<<5)	/* 1Tģʽ	*/
#define 	Timer4_12T()				T4T3M &= ~(1<<5)	/* 12Tģʽ,	default	*/
#define		Timer4_CLKO_Enable()		T4T3M |=  (1<<4)	/* ÔÊÐíT4Òç³öÂö³åÔÚT4(P0.6)½ÅÊä³ö£¬Fck = 1/2 T2 Òç³öÂÊ£¬T2¿ÉÒÔ1T»ò12T¡£	*/
#define		Timer4_CLKO_Disable()		T4T3M &= ~(1<<4)	/* ½ûÖ¹T4Òç³öÂö³åÔÚT4(P0.6)½ÅÊä³ö	*/
#define		Timer4_CLKO_Enable_P06()	T4T3M |=  (1<<4)	/* ÔÊÐíT4Òç³öÂö³åÔÚT4(P0.6)½ÅÊä³ö£¬Fck = 1/2 T2 Òç³öÂÊ£¬T2¿ÉÒÔ1T»ò12T¡£	*/
#define		Timer4_CLKO_Disable_P06()	T4T3M &= ~(1<<4)	/* ½ûÖ¹T4Òç³öÂö³åÔÚT4(P0.6)½ÅÊä³ö	*/
#define 	Timer4_InterruptEnable()	IE2  |=  (1<<6)		/* ÔÊÐíTimer4ÖжÏ.	*/
#define 	Timer4_InterruptDisable()	IE2  &= ~(1<<6)		/* ½ûÖ¹Timer4ÖжÏ.	*/

#define		T4_Load(n)					TH4 = (n) / 256,	TL4 = (n) % 256
#define		T4_Load_us_1T(n)			Timer4_AsTimer(),Timer4_1T(), TH4=(65536-((MAIN_Fosc/1000)*(n)+500)/1000)/256, TL4=(65536-((MAIN_Fosc/1000)*(n)+500)/1000)%256
#define		T4_Load_us_12T(n)			Timer4_AsTimer(),Timer4_12T(),TH4=(65536-((MAIN_Fosc/12000)*(n)+500)/1000)/256,TL4=(65536-((MAIN_Fosc/12000)*(n)+500)/1000)%256
#define		T4_Frequency_1T_P06(n)		Timer4_InterruptDisable(),Timer4_AsTimer(),Timer4_1T(), TH4=(65536-(n/2+MAIN_Fosc/2)/(n))/256, TL4=(65536-(n/2+MAIN_Fosc/2)/(n))%256, Timer4_CLKO_P06_Enable(),Timer4_Run()	/* fx=fosc/(2*M)/n,  M=1 or M=12 */
#define		T4_Frequency_12T_P06(n)		Timer4_InterruptDisable(),Timer4_AsTimer(),Timer4_12T(),TH4=(65536-(n/2+MAIN_Fosc/24)/(n))/256,TL4=(65536-(n/2+MAIN_Fosc/24)/(n))%256,Timer4_CLKO_P06_Enable(),Timer4_Run()	/* fx=fosc/(2*M)/n,  M=1 or M=12 */
//====================================================================================================================

//sfr WDT_CONTR = 0xC1; //Watch-Dog-Timer Control register
//                                      7     6     5      4       3      2   1   0     Reset Value
//                                  WDT_FLAG  -  EN_WDT CLR_WDT IDLE_WDT PS2 PS1 PS0    xx00,0000
#define D_WDT_FLAG			(1<<7)
#define D_EN_WDT			(1<<5)
#define D_CLR_WDT			(1<<4)	/* auto clear	*/
#define D_IDLE_WDT			(1<<3)	/* WDT counter when Idle	*/
#define D_WDT_SCALE_2		0
#define D_WDT_SCALE_4		1
#define D_WDT_SCALE_8		2		/* T=393216*N/fo	*/
#define D_WDT_SCALE_16		3
#define D_WDT_SCALE_32		4
#define D_WDT_SCALE_64		5
#define D_WDT_SCALE_128		6
#define D_WDT_SCALE_256		7

#define	WDT_reset(n)	WDT_CONTR = D_EN_WDT + D_CLR_WDT + D_IDLE_WDT + (n)		/* ³õʼ»¯WDT£¬Î¹¹· */


//						  7     6      5    4     3      2    1     0     Reset Value
//sfr PCON   = 0x87;	SMOD  SMOD0  LVDF  POF   GF1    GF0   PD   IDL    0001,0000	 //Power Control 
//SMOD		//´®¿ÚË«±¶ËÙ
//SMOD0
#define		LVDF		(1<<5)	/* P4.6µÍѹ¼ì²â±êÖ¾ */
//POF
//GF1
//GF0
//#define 	D_PD		2		/* set 1, power down mode */
//#define 	D_IDLE		1		/* set 1, idle mode */
#define		MCU_IDLE()			PCON |= 1	/* MCU ½øÈë IDLE ģʽ */
#define		MCU_POWER_DOWN()	PCON |= 2	/* MCU ½øÈë ˯Ãß Ä£Ê½ */


//sfr ISP_CMD   = 0xC5;
#define		ISP_STANDBY()	ISP_CMD = 0		/* ISP¿ÕÏÐÃüÁ½ûÖ¹£©*/
#define		ISP_READ()		ISP_CMD = 1		/* ISP¶Á³öÃüÁî		*/
#define		ISP_WRITE()		ISP_CMD = 2		/* ISPдÈëÃüÁî		*/
#define		ISP_ERASE()		ISP_CMD = 3		/* ISP²Á³ýÃüÁî		*/

//sfr ISP_TRIG  = 0xC6;
#define 	ISP_TRIG()	ISP_TRIG = 0x5A,	ISP_TRIG = 0xA5		/* ISP´¥·¢ÃüÁî */

//							  7    6    5      4    3    2    1     0    Reset Value
//sfr IAP_CONTR = 0xC7;		IAPEN SWBS SWRST CFAIL  -   WT2  WT1   WT0   0000,x000	//IAP Control Register
#define ISP_EN			(1<<7)
#define ISP_SWBS		(1<<6)
#define ISP_SWRST		(1<<5)
#define ISP_CMD_FAIL	(1<<4)
#define ISP_WAIT_1MHZ	7
#define ISP_WAIT_2MHZ	6
#define ISP_WAIT_3MHZ	5
#define ISP_WAIT_6MHZ	4
#define ISP_WAIT_12MHZ	3
#define ISP_WAIT_20MHZ	2
#define ISP_WAIT_24MHZ	1
#define ISP_WAIT_30MHZ	0

#if (MAIN_Fosc >= 24000000L)
	#define		ISP_WAIT_FREQUENCY	ISP_WAIT_30MHZ
#elif (MAIN_Fosc >= 20000000L)
	#define		ISP_WAIT_FREQUENCY	ISP_WAIT_24MHZ
#elif (MAIN_Fosc >= 12000000L)
	#define		ISP_WAIT_FREQUENCY	ISP_WAIT_20MHZ
#elif (MAIN_Fosc >= 6000000L)
	#define		ISP_WAIT_FREQUENCY	ISP_WAIT_12MHZ
#elif (MAIN_Fosc >= 3000000L)
	#define		ISP_WAIT_FREQUENCY	ISP_WAIT_6MHZ
#elif (MAIN_Fosc >= 2000000L)
	#define		ISP_WAIT_FREQUENCY	ISP_WAIT_3MHZ
#elif (MAIN_Fosc >= 1000000L)
	#define		ISP_WAIT_FREQUENCY	ISP_WAIT_2MHZ
#else
	#define		ISP_WAIT_FREQUENCY	ISP_WAIT_1MHZ
#endif



/* ADC Register */
//								7       6      5       4         3      2    1    0   Reset Value
//sfr ADC_CONTR = 0xBC;		ADC_POWER SPEED1 SPEED0 ADC_FLAG ADC_START CHS2 CHS1 CHS0 0000,0000	/* AD ת»»¿ØÖƼĴæÆ÷ */ 
//sfr ADC_RES  = 0xBD;		ADCV.9 ADCV.8 ADCV.7 ADCV.6 ADCV.5 ADCV.4 ADCV.3 ADCV.2	  0000,0000	/* A/D ת»»½á¹û¸ß8λ */ 
//sfr ADC_RESL = 0xBE;												  ADCV.1 ADCV.0	  0000,0000	/* A/D ת»»½á¹ûµÍ2λ */
//sfr ADC_CONTR  = 0xBC;	//Ö±½ÓÓÃMOV²Ù×÷£¬²»ÒªÓÃÓë»ò


//sfr SPCTL  = 0xCE;	SPI¿ØÖƼĴæÆ÷
//   7       6       5       4       3       2       1       0    	Reset Value
//	SSIG	SPEN	DORD	MSTR	CPOL	CPHA	SPR1	SPR0		0x00

#define	SPI_SSIG_None()		SPCTL |=  (1<<7)		/* 1: ºöÂÔSS½Å	*/
#define	SPI_SSIG_Enable()	SPCTL &= ~(1<<7)		/* 0: SS½ÅÓÃÓÚ¾ö¶¨Ö÷´Ó»ú	*/
#define	SPI_Enable()		SPCTL |=  (1<<6)		/* 1: ÔÊÐíSPI	*/
#define	SPI_Disable()		SPCTL &= ~(1<<6)		/* 0: ½ûÖ¹SPI	*/
#define	SPI_LSB_First()		SPCTL |=  (1<<5)		/* 1: LSBÏÈ·¢	*/
#define	SPI_MSB_First()		SPCTL &= ~(1<<5)		/* 0: MSBÏÈ·¢	*/
#define	SPI_Master()		SPCTL |=  (1<<4)		/* 1: ÉèΪÖ÷»ú	*/
#define	SPI_Slave()			SPCTL &= ~(1<<4)		/* 0: ÉèΪ´Ó»ú	*/
#define	SPI_SCLK_NormalH()	SPCTL |=  (1<<3)		/* 1: ¿ÕÏÐʱSCLKΪ¸ßµçƽ	*/
#define	SPI_SCLK_NormalL()	SPCTL &= ~(1<<3)		/* 0: ¿ÕÏÐʱSCLKΪµÍµçƽ	*/
#define	SPI_PhaseH()		SPCTL |=  (1<<2)		/* 1: 	*/
#define	SPI_PhaseL()		SPCTL &= ~(1<<2)		/* 0: 	*/
#define	SPI_Speed(n)		SPCTL = (SPCTL & ~3) | (n)	/*ÉèÖÃËÙ¶È, 0 -- fosc/4, 1 -- fosc/16, 2 -- fosc/64, 3 -- fosc/128	*/

//sfr SPDAT  = 0xCF; //SPI Data Register                                                     0000,0000
//sfr SPSTAT  = 0xCD;	//SPI״̬¼Ä´æÆ÷
//   7       6      5   4   3   2   1   0    	Reset Value
//	SPIF	WCOL	-	-	-	-	-	-
#define	SPIF	0x80		/* SPI´«ÊäÍê³É±êÖ¾¡£Ð´Èë1Çå0¡£*/
#define	WCOL	0x40		/* SPIд³åÍ»±êÖ¾¡£Ð´Èë1Çå0¡£  */

#define		SPI_USE_P12P13P14P15()	AUXR1 &= ~0x0c					/* ½«SPIÇл»µ½P12(SS) P13(MOSI) P14(MISO) P15(SCLK)(ÉϵçĬÈÏ)¡£*/
#define		SPI_USE_P24P23P22P21()	AUXR1 = (AUXR1 & ~0x0c) | 0x04	/* ½«SPIÇл»µ½P24(SS) P23(MOSI) P22(MISO) P21(SCLK)¡£*/
#define		SPI_USE_P54P40P41P43()	AUXR1 = (AUXR1 & ~0x0c) | 0x08	/* ½«SPIÇл»µ½P54(SS) P40(MOSI) P41(MISO) P43(SCLK)¡£*/


/*
;PCA_PWMn:    7       6     5   4   3   2     1       0
;			EBSn_1	EBSn_0	-	-	-	-	EPCnH	EPCnL
;B5-B2:		±£Áô
;B1(EPCnH):	ÔÚPWMģʽÏ£¬ÓëCCAPnH×é³É9λÊý¡£
;B0(EPCnL):	ÔÚPWMģʽÏ£¬ÓëCCAPnL×é³É9λÊý¡£
*/
#define		PWM0_NORMAL()	PCA_PWM0 &= ~2					/* PWM0Õý³£Êä³ö(ĬÈÏ)	*/
#define		PWM0_OUT_0()	PCA_PWM0 |=  2, CCAP0H = 0xff	/* PWM0Ò»Ö±Êä³ö0		*/
#define		PWM0_OUT_1()	PCA_PWM0 &= ~2, CCAP0H = 0		/* PWM0Ò»Ö±Êä³ö1		*/

#define		PWM1_NORMAL()	PCA_PWM1 &= ~2					/* PWM1Õý³£Êä³ö(ĬÈÏ)	*/
#define		PWM1_OUT_0()	PCA_PWM1 |=  2, CCAP1H = 0xff	/* PWM1Ò»Ö±Êä³ö0		*/
#define		PWM1_OUT_1()	PCA_PWM1 &= ~2, CCAP1H = 0		/* PWM1Ò»Ö±Êä³ö1		*/

#define		PWM2_NORMAL()	PCA_PWM2 &= ~2					/* PWM2Õý³£Êä³ö(ĬÈÏ)	*/
#define		PWM2_OUT_0()	PCA_PWM2 |=  2, CCAP2H = 0xff	/* PWM2Ò»Ö±Êä³ö0		*/
#define		PWM2_OUT_1()	PCA_PWM2 &= ~2, CCAP2H = 0		/* PWM2Ò»Ö±Êä³ö1		*/

#define		PWM3_NORMAL()	PCA_PWM3 &= ~2					/* PWM3Õý³£Êä³ö(ĬÈÏ)	*/
#define		PWM3_OUT_0()	PCA_PWM3 |=  2, CCAP3H = 0xff	/* PWM3Ò»Ö±Êä³ö0		*/
#define		PWM3_OUT_1()	PCA_PWM3 &= ~2, CCAP3H = 0		/* PWM3Ò»Ö±Êä³ö1		*/


//						7     6     5     4     3     2     1     0     Reset Value
//sfr CCON   = 0xD8;	CF    CR    -     -    CCF3  CCF2  CCF1  CCF0   00xx,xx00	//PCA ¿ØÖƼĴæÆ÷¡£
sbit CCF0  = CCON^0;	/* PCA Ä£¿é0ÖжϱêÖ¾£¬ÓÉÓ²¼þÖÃ룬±ØÐëÓÉÈí¼þÇå0¡£	*/
sbit CCF1  = CCON^1;	/* PCA Ä£¿é1ÖжϱêÖ¾£¬ÓÉÓ²¼þÖÃ룬±ØÐëÓÉÈí¼þÇå0¡£	*/
sbit CCF2  = CCON^2;	/* PCA Ä£¿é2ÖжϱêÖ¾£¬ÓÉÓ²¼þÖÃ룬±ØÐëÓÉÈí¼þÇå0¡£	*/
sbit CCF3  = CCON^3;	/* PCA Ä£¿é3ÖжϱêÖ¾£¬ÓÉÓ²¼þÖÃ룬±ØÐëÓÉÈí¼þÇå0¡£	*/
sbit CR    = CCON^6;	/* 1: ÔÊÐíPCA¼ÆÊýÆ÷¼ÆÊý£¬±ØÐëÓÉÈí¼þÇå0¡£*/
sbit CF    = CCON^7;	/* PCA¼ÆÊýÆ÷Òç³ö£¨CH£¬CLÓÉFFFFH±äΪ0000H£©±êÖ¾¡£PCA¼ÆÊýÆ÷Òç³öºóÓÉÓ²¼þÖÃ룬±ØÐëÓÉÈí¼þÇå0¡£*/

//					 7     6     5     4     3     2     1     0    Reset Value
//sfr CMOD  = 0xD9;	CIDL   -     -     -   CPS2   CPS1  CPS0  ECF   0xxx,0000	//PCA ¹¤×÷ģʽ¼Ä´æÆ÷¡£
#define PCA_IDLE_OFF()		CMOD |=  (1<<7)				/* IDLE״̬PCAÍ£Ö¹¼ÆÊý¡£	*/
#define PCA_IDLE_ON()		CMOD &= ~(1<<7)				/* IDLE״̬PCA¼ÌÐø¼ÆÊý¡£	*/
#define PCA_CLK_12T()		CMOD &= ~0x0E				/* PCA¼ÆÊýÂö³åÑ¡Ôñ fosc/12	*/
#define PCA_CLK_2T()		CMOD = (CMOD & ~0x0E) + 2	/* PCA¼ÆÊýÂö³åÑ¡Ôñ fosc/2	*/
#define PCA_CLK_T0()		CMOD = (CMOD & ~0x0E) + 4	/* PCA¼ÆÊýÂö³åÑ¡ÔñTimer0Öжϣ¬Timer0¿Éͨ¹ýAUXR¼Ä´æÆ÷ÉèÖóɹ¤×÷ÔÚ12T»ò1Tģʽ¡£	*/
#define PCA_CLK_ECI()		CMOD = (CMOD & ~0x0E) + 6	/* PCA¼ÆÊýÂö³åÑ¡Ôñ´ÓECI/P3.4½ÅÊäÈëµÄÍⲿʱÖÓ£¬×î´ó fosc/2¡£	*/
#define PCA_CLK_1T()		CMOD = (CMOD & ~0x0E) + 8	/* PCA¼ÆÊýÂö³åÑ¡Ôñ Fosc	*/
#define PCA_CLK_4T()		CMOD = (CMOD & ~0x0E) + 10	/* PCA¼ÆÊýÂö³åÑ¡Ôñ Fosc/4	*/
#define PCA_CLK_6T()		CMOD = (CMOD & ~0x0E) + 12	/* PCA¼ÆÊýÂö³åÑ¡Ôñ Fosc/6	*/
#define PCA_CLK_8T()		CMOD = (CMOD & ~0x0E) + 14	/* PCA¼ÆÊýÂö³åÑ¡Ôñ Fosc/8	*/
#define PCA_INT_ENABLE()	CMOD |=  1					/* PCA¼ÆÊýÆ÷Òç³öÖжÏÔÊÐí룬1---ÔÊÐíCF£¨CCON.7£©²úÉúÖжϡ£	*/
#define PCA_INT_DISABLE()	CMOD &= ~1					/* PCA¼ÆÊýÆ÷Òç³öÖжϽûÖ¹¡£	*/

//					    7      6       5        4       3       2       1      0    Reset Value
//sfr AUXR1 = 0xA2;	  S1_S1  S1_S0  CCP_S1   CCP_S0  SPI_S1   SPI_S0    -     DPS   0100,0000	//Auxiliary Register 1

#define		PCA_USE_P12P17P16P15P14()	AUXR1 &= ~0x30					/* ½«PCA/PWMÇл»µ½P12(ECI) P17(CCP0) P16(CCP1) P15(CCP2) P14(CCP3)(ÉϵçĬÈÏ) */
#define		PCA_USE_P22P23P24P25P26()	AUXR1 = (AUXR1 & ~0x30) | 0x10	/* ½«PCA/PWMÇл»µ½P22(ECI) P23(CCP0) P24(CCP1) P25(CCP2) P26(CCP3) */
#define		PCA_USE_P74P70P71P72P73()	AUXR1 = (AUXR1 & ~0x30) | 0x20	/* ½«PCA/PWMÇл»µ½P74(ECI) P70(CCP0) P71(CCP1) P72(CCP2) P73(CCP3) */
#define		PCA_USE_P35P33P32P31P30()	AUXR1 = (AUXR1 & ~0x30) | 0x30	/* ½«PCA/PWMÇл»µ½P35(ECI) P33(CCP0) P32(CCP1) P31(CCP2) P30(CCP3) */

#define		DPS_SEL1()		AUXR1 |=  1		/* 1£ºÑ¡ÔñDPTR1¡£	*/
#define		DPS_SEL0()		AUXR1 &= ~1		/* 0£ºÑ¡ÔñDPTR0(ÉϵçĬÈÏ)¡£	*/


/*									7     6       5       4     3     2     1     0     Reset Value
//sfr CCAPM0 = 0xDA;	PWM ¼Ä´æÆ÷  -   ECOM0  CCAPP0  CCAPN0  MAT0  TOG0  PWM0  ECCF0   x000,0000	//PCA Ä£¿é0
//sfr CCAPM1 = 0xDB;	PWM ¼Ä´æÆ÷  -   ECOM1  CCAPP1  CCAPN1  MAT1  TOG1  PWM1  ECCF1   x000,0000	//PCA Ä£¿é1
//sfr CCAPM2 = 0xDC;	PWM ¼Ä´æÆ÷  -   ECOM2  CCAPP2  CCAPN2  MAT2  TOG2  PWM2  ECCF2   x000,0000	//PCA Ä£¿é2
//sfr CCAPM3 = 0xDD;	PWM ¼Ä´æÆ÷  -   ECOM3  CCAPP3  CCAPN3  MAT3  TOG3  PWM3  ECCF3   x000,0000	//PCA Ä£¿é3
;ECOMn = 1:	ÔÊÐí±È½Ï¹¦ÄÜ¡£
;CAPPn = 1:	ÔÊÐíÉÏÉýÑØ´¥·¢²¶×½¹¦ÄÜ¡£
;CAPNn = 1:	ÔÊÐíϽµÑØ´¥·¢²¶×½¹¦ÄÜ¡£
;MATn  = 1:	µ±Æ¥ÅäÇé¿ö·¢Éúʱ£¬ÔÊÐíCCONÖеÄCCFnÖÃλ¡£
;TOGn  = 1:	µ±Æ¥ÅäÇé¿ö·¢Éúʱ£¬CEXn½«·­×ª¡£(CEX0/PCA0/PWM0/P3.7,CEX1/PCA1/PWM1/P3.5)
;PWMn  = 1:	½«CEXnÉèÖÃΪPWMÊä³ö¡£
;ECCFn = 1:	ÔÊÐíCCONÖеÄCCFn´¥·¢Öжϡ£
;ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
;  0     0     0    0    0    0     0		00H	δÆôÓÃÈκι¦ÄÜ¡£
;  x     1     0    0    0    0     x	 	20H	16λCEXnÉÏÉýÑØ´¥·¢²¶×½¹¦ÄÜ¡£
;  x     0     1    0    0    0     x	 	10H	16λCEXnϽµÑØ´¥·¢²¶×½¹¦ÄÜ¡£
;  x     1     1    0    0    0     x	 	30H	16λCEXn/PCAn±ßÑØ£¨ÉÏ¡¢ÏÂÑØ£©´¥·¢²¶×½¹¦ÄÜ¡£
;  1     0     0    1    0    0     x	 	48H	16λÈí¼þ¶¨Ê±Æ÷¡£
;  1     0     0    1    1    0     x	 	4CH	16λ¸ßËÙÂö³åÊä³ö¡£
;  1     0     0    0    0    1     0		42H	8λPWM¡£ÎÞÖжÏ
;  1     1     0    0    0    1     1		63H	8λPWM¡£µÍ±ä¸ß¿É²úÉúÖжÏ
;  1     0     1    0    0    1     1		53H	8λPWM¡£¸ß±äµÍ¿É²úÉúÖжÏ
;  1     1     1    0    0    1     1		73H	8λPWM¡£µÍ±ä¸ß»ò¸ß±äµÍ¾ù¿É²úÉúÖжÏ
;*******************************************************************
;*******************************************************************/
#define		PCA0_none()				CCAPM0 = 0
#define		PCA0_PWM(nbit)			CCAPM0 = 0x42,PCA_PWM0 = (PCA_PWM0 & 0x0c) | ((8-nbit)<<6)
#define		PCA0_PWM_rise_int(nbit) CCAPM0 = 0x63,PCA_PWM0 = (PCA_PWM0 & 0x0c) | ((8-nbit)<<6)
#define		PCA0_PWM_fall_int(nbit) CCAPM0 = 0x53,PCA_PWM0 = (PCA_PWM0 & 0x0c) | ((8-nbit)<<6)
#define		PCA0_PWM_edge_int(nbit) CCAPM0 = 0x73,PCA_PWM0 = (PCA_PWM0 & 0x0c) | ((8-nbit)<<6)
#define		PCA0_capture_rise()		CCAPM0 = (0x20 + 1)
#define		PCA0_capture_fall()		CCAPM0 = (0x10 + 1)
#define		PCA0_capture_edge()		CCAPM0 = (0x30 + 1)
#define		PCA0_16bit_Timer()		CCAPM0 = (0x48 + 1)
#define		PCA0_High_Pulse()		CCAPM0 = (0x4C + 1)

#define		PCA1_none()				CCAPM1 = 0
#define		PCA1_PWM(nbit)			CCAPM1 = 0x42,PCA_PWM1 = (PCA_PWM1 & 0x0c) | ((8-nbit)<<6)
#define		PCA1_PWM_rise_int(nbit) CCAPM1 = 0x63,PCA_PWM1 = (PCA_PWM1 & 0x0c) | ((8-nbit)<<6)
#define		PCA1_PWM_fall_int(nbit) CCAPM1 = 0x53,PCA_PWM1 = (PCA_PWM1 & 0x0c) | ((8-nbit)<<6)
#define		PCA1_PWM_edge_int(nbit) CCAPM1 = 0x73,PCA_PWM1 = (PCA_PWM1 & 0x0c) | ((8-nbit)<<6)
#define		PCA1_capture_rise()		CCAPM1 = (0x20 + 1)
#define		PCA1_capture_fall()		CCAPM1 = (0x10 + 1)
#define		PCA1_capture_edge()		CCAPM1 = (0x30 + 1)
#define		PCA1_16bit_Timer()		CCAPM1 = (0x48 + 1)
#define		PCA1_High_Pulse()		CCAPM1 = (0x4C + 1)

#define		PCA2_none()				CCAPM2 = 0
#define		PCA2_PWM(nbit)			CCAPM2 = 0x42,PCA_PWM2 = (PCA_PWM2 & 0x0c) | ((8-nbit)<<6)
#define		PCA2_PWM_rise_int(nbit) CCAPM2 = 0x63,PCA_PWM2 = (PCA_PWM2 & 0x0c) | ((8-nbit)<<6)
#define		PCA2_PWM_fall_int(nbit) CCAPM2 = 0x53,PCA_PWM2 = (PCA_PWM2 & 0x0c) | ((8-nbit)<<6)
#define		PCA2_PWM_edge_int(nbit) CCAPM2 = 0x73,PCA_PWM2 = (PCA_PWM2 & 0x0c) | ((8-nbit)<<6)
#define		PCA2_capture_rise()		CCAPM2 = (0x20 + 1)
#define		PCA2_capture_fall()		CCAPM2 = (0x10 + 1)
#define		PCA2_capture_edge()		CCAPM2 = (0x30 + 1)
#define		PCA2_16bit_Timer()		CCAPM2 = (0x48 + 1)
#define		PCA2_High_Pulse()		CCAPM2 = (0x4C + 1)

#define		PCA3_none()				CCAPM3 = 0
#define		PCA3_PWM(nbit)			CCAPM3 = 0x42,PCA_PWM2 = (PCA_PWM2 & 0x0c) | ((8-nbit)<<6)
#define		PCA3_PWM_rise_int(nbit) CCAPM3 = 0x63,PCA_PWM2 = (PCA_PWM2 & 0x0c) | ((8-nbit)<<6)
#define		PCA3_PWM_fall_int(nbit) CCAPM3 = 0x53,PCA_PWM2 = (PCA_PWM2 & 0x0c) | ((8-nbit)<<6)
#define		PCA3_PWM_edge_int(nbit) CCAPM3 = 0x73,PCA_PWM2 = (PCA_PWM2 & 0x0c) | ((8-nbit)<<6)
#define		PCA3_capture_rise()		CCAPM3 = (0x20 + 1)
#define		PCA3_capture_fall()		CCAPM3 = (0x10 + 1)
#define		PCA3_capture_edge()		CCAPM3 = (0x30 + 1)
#define		PCA3_16bit_Timer()		CCAPM3 = (0x48 + 1)
#define		PCA3_High_Pulse()		CCAPM3 = (0x4C + 1)


/**********************************************************/
typedef 	unsigned char	u8;
typedef 	unsigned int	u16;
typedef 	unsigned long	u32;

/**********************************************************/
#define NOP1()  _nop_()
#define NOP2()  NOP1(),NOP1()
#define NOP3()  NOP2(),NOP1()
#define NOP4()  NOP3(),NOP1()
#define NOP5()  NOP4(),NOP1()
#define NOP6()  NOP5(),NOP1()
#define NOP7()  NOP6(),NOP1()
#define NOP8()  NOP7(),NOP1()
#define NOP9()  NOP8(),NOP1()
#define NOP10() NOP9(),NOP1()
#define NOP11() NOP10(),NOP1()
#define NOP12() NOP11(),NOP1()
#define NOP13() NOP12(),NOP1()
#define NOP14() NOP13(),NOP1()
#define NOP15() NOP14(),NOP1()
#define NOP16() NOP15(),NOP1()
#define NOP17() NOP16(),NOP1()
#define NOP18() NOP17(),NOP1()
#define NOP19() NOP18(),NOP1()
#define NOP20() NOP19(),NOP1()
#define NOP21() NOP20(),NOP1()
#define NOP22() NOP21(),NOP1()
#define NOP23() NOP22(),NOP1()
#define NOP24() NOP23(),NOP1()
#define NOP25() NOP24(),NOP1()
#define NOP26() NOP25(),NOP1()
#define NOP27() NOP26(),NOP1()
#define NOP28() NOP27(),NOP1()
#define NOP29() NOP28(),NOP1()
#define NOP30() NOP29(),NOP1()
#define NOP31() NOP30(),NOP1()
#define NOP32() NOP31(),NOP1()
#define NOP33() NOP32(),NOP1()
#define NOP34() NOP33(),NOP1()
#define NOP35() NOP34(),NOP1()
#define NOP36() NOP35(),NOP1()
#define NOP37() NOP36(),NOP1()
#define NOP38() NOP37(),NOP1()
#define NOP39() NOP38(),NOP1()
#define NOP40() NOP39(),NOP1()
#define NOP(N)  NOP##N()


/**********************************************/
#define P0n_standard(bitn)			P0M1 &= ~(bitn),	P0M0 &= ~(bitn)	/* 00  */
#define P0n_push_pull(bitn)			P0M1 &= ~(bitn),	P0M0 |=  (bitn)	/* 01  */
#define P0n_pure_input(bitn)		P0M1 |=  (bitn),	P0M0 &= ~(bitn)	/* 10  */
#define P0n_open_drain(bitn)		P0M1 |=  (bitn),	P0M0 |=  (bitn)	/* 11  */

#define P1n_standard(bitn)			P1M1 &= ~(bitn),	P1M0 &= ~(bitn)
#define P1n_push_pull(bitn)			P1M1 &= ~(bitn),	P1M0 |=  (bitn)
#define P1n_pure_input(bitn)		P1M1 |=  (bitn),	P1M0 &= ~(bitn)
#define P1n_open_drain(bitn)		P1M1 |=  (bitn),	P1M0 |=  (bitn)

#define P2n_standard(bitn)			P2M1 &= ~(bitn),	P2M0 &= ~(bitn)
#define P2n_push_pull(bitn)			P2M1 &= ~(bitn),	P2M0 |=  (bitn)
#define P2n_pure_input(bitn)		P2M1 |=  (bitn),	P2M0 &= ~(bitn)
#define P2n_open_drain(bitn)		P2M1 |=  (bitn),	P2M0 |=  (bitn)

#define P3n_standard(bitn)			P3M1 &= ~(bitn),	P3M0 &= ~(bitn)
#define P3n_push_pull(bitn)			P3M1 &= ~(bitn),	P3M0 |=  (bitn)
#define P3n_pure_input(bitn)		P3M1 |=  (bitn),	P3M0 &= ~(bitn)
#define P3n_open_drain(bitn)		P3M1 |=  (bitn),	P3M0 |=  (bitn)

#define P4n_standard(bitn)			P4M1 &= ~(bitn),	P4M0 &= ~(bitn)
#define P4n_push_pull(bitn)			P4M1 &= ~(bitn),	P4M0 |=  (bitn)
#define P4n_pure_input(bitn)		P4M1 |=  (bitn),	P4M0 &= ~(bitn)
#define P4n_open_drain(bitn)		P4M1 |=  (bitn),	P4M0 |=  (bitn)

#define P5n_standard(bitn)			P5M1 &= ~(bitn),	P5M0 &= ~(bitn)
#define P5n_push_pull(bitn)			P5M1 &= ~(bitn),	P5M0 |=  (bitn)
#define P5n_pure_input(bitn)		P5M1 |=  (bitn),	P5M0 &= ~(bitn)
#define P5n_open_drain(bitn)		P5M1 |=  (bitn),	P5M0 |=  (bitn)

#define P6n_standard(bitn)			P6M1 &= ~(bitn),	P6M0 &= ~(bitn)
#define P6n_push_pull(bitn)			P6M1 &= ~(bitn),	P6M0 |=  (bitn)
#define P6n_pure_input(bitn)		P6M1 |=  (bitn),	P6M0 &= ~(bitn)
#define P6n_open_drain(bitn)		P6M1 |=  (bitn),	P6M0 |=  (bitn)

#define P7n_standard(bitn)			P7M1 &= ~(bitn),	P7M0 &= ~(bitn)
#define P7n_push_pull(bitn)			P7M1 &= ~(bitn),	P7M0 |=  (bitn)
#define P7n_pure_input(bitn)		P7M1 |=  (bitn),	P7M0 &= ~(bitn)
#define P7n_open_drain(bitn)		P7M1 |=  (bitn),	P7M0 |=  (bitn)


/****************************************************************/


//sfr INT_CLKO = 0x8F;	//¸½¼ÓµÄ SFR WAKE_CLKO (µØÖ·£º0x8F)
/*
    7   6    5    4   3     2        1       0         Reset Value
    -  EX4  EX3  EX2  -   T2CLKO   T1CLKO  T0CLKO      0000,0000B
b6 -  EX4      : ÍâÖжÏINT4ÔÊÐí
b5 -  EX3      : ÍâÖжÏINT3ÔÊÐí
b4 -  EX2      : ÍâÖжÏINT2ÔÊÐí
b2 - T1CLKO    : ÔÊÐí T2 Òç³öÂö³åÔÚP3.0½ÅÊä³ö£¬Fck1 = 1/2 T1 Òç³öÂÊ
b1 - T1CLKO    : ÔÊÐí T1 Òç³öÂö³åÔÚP3.4½ÅÊä³ö£¬Fck1 = 1/2 T1 Òç³öÂÊ
b0 - T0CLKO    : ÔÊÐí T0 Òç³öÂö³åÔÚP3.5½ÅÊä³ö£¬Fck0 = 1/2 T0 Òç³öÂÊ
*/

#define		LVD_InterruptEnable()		ELVD = 1
#define		LVD_InterruptDisable()		ELVD = 0


//sfr WKTCL = 0xAA;	//STC11F\10ºÍSTC15ϵÁÐ »½ÐѶ¨Ê±Æ÷µÍ×Ö½Ú
//sfr WKTCH = 0xAB;	//STC11F\10ºÍSTC15ϵÁÐ »½ÐѶ¨Ê±Æ÷¸ß×Ö½Ú
//	B7		B6	B5	B4	B3	B2	B1	B0		B7	B6	B5	B4	B3	B2	B1	B0
//	WKTEN				S11	S10	S9	S8		S7	S6	S5	S4	S3	S2	S1	S0	n * 560us
#define		WakeTimerDisable()		WKTCH &= 0x7f	/* WKTEN = 0		½ûֹ˯Ãß»½ÐѶ¨Ê±Æ÷ */
#define		WakeTimerSet(scale)		WKTCL = (scale) % 256,WKTCH = (scale) / 256 | 0x80	/* WKTEN = 1	ÔÊÐí˯Ãß»½ÐѶ¨Ê±Æ÷ */



//sfr BUS_SPEED = 0xA1; //Stretch register      -   -  -  -   -   -  EXRTS1  EXRTSS0 xxxx,xx10
#define		BUS_SPEED_1T()	BUS_SPEED = 0
#define		BUS_SPEED_2T()	BUS_SPEED = 1
#define		BUS_SPEED_4T()	BUS_SPEED = 2
#define		BUS_SPEED_8T()	BUS_SPEED = 3

/*   interrupt vector */
#define		INT0_VECTOR		0
#define		TIMER0_VECTOR	1
#define		INT1_VECTOR		2
#define		TIMER1_VECTOR	3
#define		UART1_VECTOR	4
#define		ADC_VECTOR		5
#define		LVD_VECTOR		6
#define		PCA_VECTOR		7
#define		UART2_VECTOR	8
#define		SPI_VECTOR		9
#define		INT2_VECTOR		10
#define		INT3_VECTOR		11
#define		TIMER2_VECTOR	12
#define		INT4_VECTOR		16
#define		UART3_VECTOR	17
#define		UART4_VECTOR	18
#define		TIMER3_VECTOR	19
#define		TIMER4_VECTOR	20
#define		CMP_VECTOR		21
#define		PWM_VECTOR		22
#define		PWMFD_VECTOR	23
#define		I2C_VECTOR		24


#define	TRUE	1
#define	FALSE	0

//=============================================================

//========================================

#define	PolityLow			0	//µÍÓÅÏȼ¶ÖжÏ
#define	PolityHigh			1	//¸ßÓÅÏȼ¶ÖжÏ

//========================================

#define		ENABLE		1
#define		DISABLE		0

#define		STC15F_L2K08S2	8
#define		STC15F_L2K16S2	16
#define		STC15F_L2K24S2	24
#define		STC15F_L2K32S2	32
#define		STC15F_L2K40S2	40
#define		STC15F_L2K48S2	48
#define		STC15F_L2K56S2	56
#define		STC15F_L2K60S2	60
#define		IAP15F_L2K61S2	61

#endif