【基带开发】AD9361 生成1到223的递增数据

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2022/06/29 17:50:56
// Design Name: 
// Module Name: gen_Incremental_223
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module gen_Incremental_223(
    clk,
    rst,
    dout,
    dout_clk_p,
    dout_en
);
    input clk,rst;
    output [7:0] dout;
    output dout_clk_p;
    output dout_en;

wire start;
    
clk_file 
#(.FREQUENCY_CLK(32'd195    ))  //5hz 
CLK_GENS(
    .clk(clk                ),
    .rst(rst                ),
    
    .clk_gens1(             ),
    .clk_gens1_p(start      )
);

reg [15:0] cnts;
always @ (posedge clk or posedge rst)
begin
    if(rst)
    begin
    cnts <= 16'hffff;
    end
    
    else if (start)
    begin
    cnts <= 16'd0;
    end
    
    else if (cnts < 16'd250) 
    begin
    cnts <= cnts + 1'b1;
    end
    
    else
    begin
    cnts <= cnts;
    end
end

reg [7:0] dout;
always @ (posedge clk or posedge rst)
begin
    if(rst)
    begin
    dout <= 8'd0;
    end
    
    else if (start)
    begin
    dout <= 8'd0;
    end
    
    else if (cnts < 16'd224) 
    begin
    dout <= dout + 1'b1;
    end
    
    else
    begin
    dout <= dout;
    end
end

reg dout_clk_p;
always @ (posedge clk or posedge rst)
begin
    if(rst)
    begin
    dout_clk_p <= 1'b0;
    end
    
    else if (start)
    begin
    dout_clk_p <= 1'b0;
    end
    
    else if (cnts < 16'd1)
    begin
    dout_clk_p <= 1'b1;
    end
    
    else
    begin
    dout_clk_p <= 1'b0;
    end
end

reg dout_en;
always @ (posedge clk or posedge rst)
begin
    if(rst)
    begin
    dout_en <= 1'b0;
    end
    
    else if (start)
    begin
    dout_en <= 1'b0;
    end
    
    else if (cnts < 16'd223)
    begin
    dout_en <= 1'b1;
    end
    
    else
    begin
    dout_en <= 1'b0;
    end
end
    
endmodule

结果