裸机程序指令集
本文主要对之前的裸机程序综合，从而实现裸机指令集项目。
项目简介：打印简易的linux界面，实现指令操控裸机程序
项目硬件：S5PV210开发版，串口线，SD卡
项目内容:
1.模拟210启动方式，实现本项目程序加载过程
210在启动过程：上电读取BL0程序，BL0实现观看门狗，初始化时钟，初始化堆和栈，判断启动方式（SD卡或Uart或USB启动）等并且读取代码BL1(16KB）到iSRAM，运行BL1代码来初始化NandFlash，再读取BL2到IRAM运行代码初始化DRAM,将OS读到DRAM,启动OS
项目程序启动：上电读取BL1，BL1（16KB）打开软开关，管看门狗，打开icache,设置SVC栈，初始化SDRAM，读取BL2到SDRAM，BL2实现linux界面和指令集
2.模拟uboot启动延时和环境变量
使用中断程序模拟uboot启动延时，以及环境变量增删改查
3.指令集实现(包含命令提示)
LED灯开关：led on|off
ADC采样：adc sample
蜂鸣器开关：buzzer on|off
lcd：
划线（（x1,y1）,(x2,y2)两点）：lcd line x1 y1 x2 y2
画圆（圆心（x1,y1），半径r）：lcd circle x1 y1 r
打印字符串(data 为要打印的字符串)：lcd string data
env(环境变量)：
打印环境变量：env print
修改/添加环境变量(已经存在该变量则修改，否则添加该变量)：env set env_name env_val
删除环境变量:env delete env_name
项目结果示例（不包含硬件结果：lcd，buzzer，led）：
项目文件:
项目代码示例：
Makefile（主）
all:
make -C ./bl1
make -C ./bl2
clean:
make clean -C ./bl1
make clean -C ./bl2write2sd(SD卡烧录脚本)
#!/bin/sh
dd iflag=dsync oflag=dsync if=./bl1/sd1.bin of=/dev/sdb seek=1
dd iflag=dsync oflag=dsync if=./bl2/sd2.bin of=/dev/sdb seek=45bl1:
start.S
#define WTCON 0xE2700000
#define SVC_STACK 0xd0037d80
#define SOFT_SW 0xE010E81C
.global _start
_start:
//set soft switcher,mean set XEINT[0] as PS_HOLD_OUT_EN,set output high level
ldr r0, =SOFT_SW
ldr r1, [r0]
orr r1, r1, #0x300
orr r1, r1, #0x01
str r1, [r0]
//close WatchDog
ldr r0,=WTCON
ldr r1,=0x0
str r1,[r0]
//init SVC stack
ldr sp,=SVC_STACK
//init icache
mrc p15,0,r0,c1,c0,0
bic r0,r0,#(1<<12) //close icache
orr r0,r0,#(1<<12) //open icache
mcr p15,0,r0,c1,c0,0
bl sdram_asm_init
//use func
bl copy_bl2_2_ddr
b .sdram_init.S
#include "s5pv210.h"
#if 1
#define DMC0_MEMCONTROL 0x00202400 // MemControl BL=4, 1Chip, DDR2 Type, dynamic self refresh, force precharge, dynamic power down off
#define DMC0_MEMCONFIG_0 0x20F01323 // MemConfig0 256MB config, 8 banks,Mapping Method[12:15]0:linear, 1:linterleaved, 2:Mixed
#define DMC0_MEMCONFIG_1 0x30F00312 // MemConfig1 默认值
#define DMC0_TIMINGA_REF 0x00000618 // TimingAref 7.8us*133MHz=1038(0x40E), 100MHz=780(0x30C), 20MHz=156(0x9C), 10MHz=78(0x4E)
#define DMC0_TIMING_ROW 0x28233287 // TimingRow for @200MHz
#define DMC0_TIMING_DATA 0x23240304 // TimingData CL=3
#define DMC0_TIMING_PWR 0x09C80232 // TimingPower
#define DMC1_MEMCONTROL 0x00202400 // MemControl BL=4, 2 chip, DDR2 type, dynamic self refresh, force precharge, dynamic power down off
#define DMC1_MEMCONFIG_0 0x40F01323 // MemConfig0 512MB config, 8 banks,Mapping Method[12:15]0:linear, 1:linterleaved, 2:Mixed
#define DMC1_MEMCONFIG_1 0x60E00312 // MemConfig1
#define DMC1_TIMINGA_REF 0x00000618 // TimingAref 7.8us*133MHz=1038(0x40E), 100MHz=780(0x30C), 20MHz=156(0x9C), 10MHz=78(0x4
#define DMC1_TIMING_ROW 0x28233289 // TimingRow for @200MHz
#define DMC1_TIMING_DATA 0x23240304 // TimingData CL=3
#define DMC1_TIMING_PWR 0x08280232 // TimingPower
#endif
#if 0
#define DMC0_MEMCONTROL 0x00212400 // MemControl BL=4, 1Chip, DDR2 Type, dynamic self refresh, force precharge, dynamic power down off
#define DMC0_MEMCONFIG_0 0x20E01323 // MemConfig0 512MB config, 8 banks,Mapping Method[12:15]0:linear, 1:linterleaved, 2:Mixed
#define DMC0_MEMCONFIG_1 0x40F01323 // MemConfig1
#define DMC0_TIMINGA_REF 0x00000618 // TimingAref 7.8us*133MHz=1038(0x40E), 100MHz=780(0x30C), 20MHz=156(0x9C), 10MHz=78(0x4E)
#define DMC0_TIMING_ROW 0x28233287 // TimingRow for @200MHz
#define DMC0_TIMING_DATA 0x23240304 // TimingData CL=3
#define DMC0_TIMING_PWR 0x09C80232 // TimingPower
#define DMC1_MEMCONTROL 0x00202400 // MemControl BL=4, 2 chip, DDR2 type, dynamic self refresh, force precharge, dynamic power down off
#define DMC1_MEMCONFIG_0 0x40C01323 // MemConfig0 512MB config, 8 banks,Mapping Method[12:15]0:linear, 1:linterleaved, 2:Mixed
#define DMC1_MEMCONFIG_1 0x00E01323 // MemConfig1
#define DMC1_TIMINGA_REF 0x00000618 // TimingAref 7.8us*133MHz=1038(0x40E), 100MHz=780(0x30C), 20MHz=156(0x9C), 10MHz=78(0x4
#define DMC1_TIMING_ROW 0x28233289 // TimingRow for @200MHz
#define DMC1_TIMING_DATA 0x23240304 // TimingData CL=3
#define DMC1_TIMING_PWR 0x08280232 // TimingPower
#endif
.global sdram_asm_init
sdram_asm_init:
ldr r0, =0xf1e00000
ldr r1, =0x0
str r1, [r0, #0x0]
/* DMC0 Drive Strength (Setting 2X) */
ldr r0, =ELFIN_GPIO_BASE
ldr r1, =0x0000AAAA
str r1, [r0, #MP1_0DRV_SR_OFFSET] // 寄存器中对应0b10，就是2X
ldr r1, =0x0000AAAA
str r1, [r0, #MP1_1DRV_SR_OFFSET]
ldr r1, =0x0000AAAA
str r1, [r0, #MP1_2DRV_SR_OFFSET]
ldr r1, =0x0000AAAA
str r1, [r0, #MP1_3DRV_SR_OFFSET]
ldr r1, =0x0000AAAA
str r1, [r0, #MP1_4DRV_SR_OFFSET]
ldr r1, =0x0000AAAA
str r1, [r0, #MP1_5DRV_SR_OFFSET]
ldr r1, =0x0000AAAA
str r1, [r0, #MP1_6DRV_SR_OFFSET]
ldr r1, =0x0000AAAA
str r1, [r0, #MP1_7DRV_SR_OFFSET]
ldr r1, =0x00002AAA
str r1, [r0, #MP1_8DRV_SR_OFFSET]
/* DMC1 Drive Strength (Setting 2X) */
ldr r0, =ELFIN_GPIO_BASE
ldr r1, =0x0000AAAA
str r1, [r0, #MP2_0DRV_SR_OFFSET]
ldr r1, =0x0000AAAA
str r1, [r0, #MP2_1DRV_SR_OFFSET]
ldr r1, =0x0000AAAA
str r1, [r0, #MP2_2DRV_SR_OFFSET]
ldr r1, =0x0000AAAA
str r1, [r0, #MP2_3DRV_SR_OFFSET]
ldr r1, =0x0000AAAA
str r1, [r0, #MP2_4DRV_SR_OFFSET]
ldr r1, =0x0000AAAA
str r1, [r0, #MP2_5DRV_SR_OFFSET]
ldr r1, =0x0000AAAA
str r1, [r0, #MP2_6DRV_SR_OFFSET]
ldr r1, =0x0000AAAA
str r1, [r0, #MP2_7DRV_SR_OFFSET]
ldr r1, =0x00002AAA
str r1, [r0, #MP2_8DRV_SR_OFFSET]
/* DMC0 initialization at single Type*/
ldr r0, =APB_DMC_0_BASE
ldr r1, =0x00101000 @PhyControl0 DLL parameter setting, manual 0x00101000
str r1, [r0, #DMC_PHYCONTROL0]
ldr r1, =0x00000086 @PhyControl1 DLL parameter setting, LPDDR/LPDDR2 Case
str r1, [r0, #DMC_PHYCONTROL1]
ldr r1, =0x00101002 @PhyControl0 DLL on
str r1, [r0, #DMC_PHYCONTROL0]
ldr r1, =0x00101003 @PhyControl0 DLL start
str r1, [r0, #DMC_PHYCONTROL0]
find_lock_val:
ldr r1, [r0, #DMC_PHYSTATUS] @Load Phystatus register value
and r2, r1, #0x7
cmp r2, #0x7 @Loop until DLL is locked
bne find_lock_val
and r1, #0x3fc0
mov r2, r1, LSL #18
orr r2, r2, #0x100000
orr r2 ,r2, #0x1000
orr r1, r2, #0x3 @Force Value locking
str r1, [r0, #DMC_PHYCONTROL0]
#if 0 /* Memory margin test 10.01.05 */
orr r1, r2, #0x1 @DLL off
str r1, [r0, #DMC_PHYCONTROL0]
#endif
/* setting DDR2 */
ldr r1, =0x0FFF2010 @ConControl auto refresh off
str r1, [r0, #DMC_CONCONTROL]
ldr r1, =DMC0_MEMCONTROL @MemControl BL=4, 1 chip, DDR2 type, dynamic self refresh, force precharge, dynamic power down off
str r1, [r0, #DMC_MEMCONTROL]
ldr r1, =DMC0_MEMCONFIG_0 @MemConfig0 256MB config, 8 banks,Mapping Method[12:15]0:linear, 1:linterleaved, 2:Mixed
str r1, [r0, #DMC_MEMCONFIG0]
ldr r1, =DMC0_MEMCONFIG_1 @MemConfig1
str r1, [r0, #DMC_MEMCONFIG1]
ldr r1, =0xFF000000 @PrechConfig
str r1, [r0, #DMC_PRECHCONFIG]
ldr r1, =DMC0_TIMINGA_REF @TimingAref 7.8us*133MHz=1038(0x40E), 100MHz=780(0x30C), 20MHz=156(0x9C), 10MHz=78(0x4E)
str r1, [r0, #DMC_TIMINGAREF]
ldr r1, =DMC0_TIMING_ROW @TimingRow for @200MHz
str r1, [r0, #DMC_TIMINGROW]
ldr r1, =DMC0_TIMING_DATA @TimingData CL=3
str r1, [r0, #DMC_TIMINGDATA]
ldr r1, =DMC0_TIMING_PWR @TimingPower
str r1, [r0, #DMC_TIMINGPOWER]
ldr r1, =0x07000000 @DirectCmd chip0 Deselect
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x01000000 @DirectCmd chip0 PALL
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00020000 @DirectCmd chip0 EMRS2
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00030000 @DirectCmd chip0 EMRS3
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00010400 @DirectCmd chip0 EMRS1 (MEM DLL on, DQS# disable)
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00000542 @DirectCmd chip0 MRS (MEM DLL reset) CL=4, BL=4
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x01000000 @DirectCmd chip0 PALL
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x05000000 @DirectCmd chip0 REFA
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x05000000 @DirectCmd chip0 REFA
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00000442 @DirectCmd chip0 MRS (MEM DLL unreset)
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00010780 @DirectCmd chip0 EMRS1 (OCD default)
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00010400 @DirectCmd chip0 EMRS1 (OCD exit)
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x07100000 @DirectCmd chip1 Deselect
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x01100000 @DirectCmd chip1 PALL
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00120000 @DirectCmd chip1 EMRS2
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00130000 @DirectCmd chip1 EMRS3
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00110400 @DirectCmd chip1 EMRS1 (MEM DLL on, DQS# disable)
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00100542 @DirectCmd chip1 MRS (MEM DLL reset) CL=4, BL=4
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x01100000 @DirectCmd chip1 PALL
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x05100000 @DirectCmd chip1 REFA
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x05100000 @DirectCmd chip1 REFA
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00100442 @DirectCmd chip1 MRS (MEM DLL unreset)
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00110780 @DirectCmd chip1 EMRS1 (OCD default)
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00110400 @DirectCmd chip1 EMRS1 (OCD exit)
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x0FF02030 @ConControl auto refresh on
str r1, [r0, #DMC_CONCONTROL]
ldr r1, =0xFFFF00FF @PwrdnConfig
str r1, [r0, #DMC_PWRDNCONFIG]
ldr r1, =0x00202400 @MemControl BL=4, 2 chip, DDR2 type, dynamic self refresh, force precharge, dynamic power down off
str r1, [r0, #DMC_MEMCONTROL]
// 上面是DRAM0初始化步骤
/*******************************************************************************************/
// 下面是DRAM1初始化步骤，两者没有联系，是并列的。
/* DMC1 initialization */
ldr r0, =APB_DMC_1_BASE
ldr r1, =0x00101000 @Phycontrol0 DLL parameter setting
str r1, [r0, #DMC_PHYCONTROL0]
ldr r1, =0x00000086 @Phycontrol1 DLL parameter setting
str r1, [r0, #DMC_PHYCONTROL1]
ldr r1, =0x00101002 @PhyControl0 DLL on
str r1, [r0, #DMC_PHYCONTROL0]
ldr r1, =0x00101003 @PhyControl0 DLL start
str r1, [r0, #DMC_PHYCONTROL0]
find_lock_val1:
ldr r1, [r0, #DMC_PHYSTATUS] @Load Phystatus register value
and r2, r1, #0x7
cmp r2, #0x7 @Loop until DLL is locked
bne find_lock_val1
and r1, #0x3fc0
mov r2, r1, LSL #18
orr r2, r2, #0x100000
orr r2, r2, #0x1000
orr r1, r2, #0x3 @Force Value locking
str r1, [r0, #DMC_PHYCONTROL0]
#if 0 /* Memory margin test 10.01.05 */
orr r1, r2, #0x1 @DLL off
str r1, [r0, #DMC_PHYCONTROL0]
#endif
/* settinf fot DDR2 */
ldr r0, =APB_DMC_1_BASE
ldr r1, =0x0FFF2010 @auto refresh off
str r1, [r0, #DMC_CONCONTROL]
ldr r1, =DMC1_MEMCONTROL @MemControl BL=4, 2 chip, DDR2 type, dynamic self refresh, force precharge, dynamic power down off
str r1, [r0, #DMC_MEMCONTROL]
ldr r1, =DMC1_MEMCONFIG_0 @MemConfig0 512MB config, 8 banks,Mapping Method[12:15]0:linear, 1:linterleaved, 2:Mixed
str r1, [r0, #DMC_MEMCONFIG0]
ldr r1, =DMC1_MEMCONFIG_1 @MemConfig1
str r1, [r0, #DMC_MEMCONFIG1]
ldr r1, =0xFF000000
str r1, [r0, #DMC_PRECHCONFIG]
ldr r1, =DMC1_TIMINGA_REF @TimingAref 7.8us*133MHz=1038(0x40E), 100MHz=780(0x30C), 20MHz=156(0x9C), 10MHz=78(0x4
str r1, [r0, #DMC_TIMINGAREF]
ldr r1, =DMC1_TIMING_ROW @TimingRow for @200MHz
str r1, [r0, #DMC_TIMINGROW]
ldr r1, =DMC1_TIMING_DATA @TimingData CL=3
str r1, [r0, #DMC_TIMINGDATA]
ldr r1, =DMC1_TIMING_PWR @TimingPower
str r1, [r0, #DMC_TIMINGPOWER]
ldr r1, =0x07000000 @DirectCmd chip0 Deselect
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x01000000 @DirectCmd chip0 PALL
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00020000 @DirectCmd chip0 EMRS2
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00030000 @DirectCmd chip0 EMRS3
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00010400 @DirectCmd chip0 EMRS1 (MEM DLL on, DQS# disable)
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00000542 @DirectCmd chip0 MRS (MEM DLL reset) CL=4, BL=4
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x01000000 @DirectCmd chip0 PALL
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x05000000 @DirectCmd chip0 REFA
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x05000000 @DirectCmd chip0 REFA
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00000442 @DirectCmd chip0 MRS (MEM DLL unreset)
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00010780 @DirectCmd chip0 EMRS1 (OCD default)
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00010400 @DirectCmd chip0 EMRS1 (OCD exit)
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x07100000 @DirectCmd chip1 Deselect
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x01100000 @DirectCmd chip1 PALL
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00120000 @DirectCmd chip1 EMRS2
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00130000 @DirectCmd chip1 EMRS3
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00110440 @DirectCmd chip1 EMRS1 (MEM DLL on, DQS# disable)
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00100542 @DirectCmd chip1 MRS (MEM DLL reset) CL=4, BL=4
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x01100000 @DirectCmd chip1 PALL
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x05100000 @DirectCmd chip1 REFA
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x05100000 @DirectCmd chip1 REFA
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00100442 @DirectCmd chip1 MRS (MEM DLL unreset)
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00110780 @DirectCmd chip1 EMRS1 (OCD default)
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x00110400 @DirectCmd chip1 EMRS1 (OCD exit)
str r1, [r0, #DMC_DIRECTCMD]
ldr r1, =0x0FF02030 @ConControl auto refresh on
str r1, [r0, #DMC_CONCONTROL]
ldr r1, =0xFFFF00FF @PwrdnConfig
str r1, [r0, #DMC_PWRDNCONFIG]
ldr r1, =DMC1_MEMCONTROL @MemControl BL=4, 2 chip, DDR2 type, dynamic self refresh, force precharge, dynamic power down off
str r1, [r0, #DMC_MEMCONTROL]
// 函数返回
mov pc, lrs5pv210.h
/* S5PC110 device base addresses */
#define ELFIN_DMA_BASE 0xE0900000
#define ELFIN_LCD_BASE 0xF8000000
#define ELFIN_USB_HOST_BASE 0xEC200000
#define ELFIN_I2C_BASE 0xE1800000
#define ELFIN_I2S_BASE 0xE2100000
#define ELFIN_ADC_BASE 0xE1700000
#define ELFIN_SPI_BASE 0xE1300000
#define ELFIN_HSMMC_0_BASE 0xEB000000
#define ELFIN_HSMMC_1_BASE 0xEB100000
#define ELFIN_HSMMC_2_BASE 0xEB200000
#define ELFIN_HSMMC_3_BASE 0xEB300000
#define ELFIN_CLOCK_POWER_BASE 0xE0100000
#define IO_RET_REL ((1 << 31) | (1 << 29) | (1 << 28))
/* Clock & Power Controller for s5pc110*/
#define APLL_LOCK_OFFSET 0x00
#define MPLL_LOCK_OFFSET 0x08
#define EPLL_LOCK_OFFSET 0x10
#define VPLL_LOCK_OFFSET 0x20
#define APLL_CON0_OFFSET 0x100
#define APLL_CON1_OFFSET 0x104
#define MPLL_CON_OFFSET 0x108
#define EPLL_CON_OFFSET 0x110
#define VPLL_CON_OFFSET 0x120
#define CLK_SRC0_OFFSET 0x200
#define CLK_SRC1_OFFSET 0x204
#define CLK_SRC2_OFFSET 0x208
#define CLK_SRC3_OFFSET 0x20c
#define CLK_SRC4_OFFSET 0x210
#define CLK_SRC5_OFFSET 0x214
#define CLK_SRC6_OFFSET 0x218
#define CLK_SRC_MASK0_OFFSET 0x280
#define CLK_SRC_MASK1_OFFSET 0x284
#define CLK_DIV0_OFFSET 0x300
#define CLK_DIV1_OFFSET 0x304
#define CLK_DIV2_OFFSET 0x308
#define CLK_DIV3_OFFSET 0x30c
#define CLK_DIV4_OFFSET 0x310
#define CLK_DIV5_OFFSET 0x314
#define CLK_DIV6_OFFSET 0x318
#define CLK_DIV7_OFFSET 0x31c
#define CLK_GATE_IP0_OFFSET 0x460
#define CLK_GATE_IP1_OFFSET 0x464
#define CLK_GATE_IP2_OFFSET 0x468
#define CLK_GATE_IP3_OFFSET 0x46c
#define CLK_GATE_IP4_OFFSET 0x470
#define CLK_GATE_BLOCK_OFFSET 0x480
#define CLK_OUT_OFFSET 0x500
#define CLK_DIV_STAT0_OFFSET 0x1000
#define CLK_DIV_STAT1_OFFSET 0x1004
#define CLK_MUX_STAT0_OFFSET 0x1100
#define CLK_MUX_STAT1_OFFSET 0x1104
#define SW_RST_OFFSET 0x2000
#define ONEDRAM_CFG_OFFSET 0x6208
#define OSC_CON_OFFSET 0x8000
#define RST_STAT_OFFSET 0xa000
#define PWR_CFG_OFFSET 0xc000
#define EINT_WAKEUP_MASK_OFFSET 0xc004
#define WAKEUP_MASK_OFFSET 0xc008
#define NORMAL_CFG_OFFSET 0xc010
#define IDLE_CFG_OFFSET 0xc020
#define STOP_CFG_OFFSET 0xc030
#define STOP_MEM_CFG_OFFSET 0xc034
#define SLEEP_CFG_OFFSET 0xc040
#define OSC_FREQ_OFFSET 0xc100
#define OSC_STABLE_OFFSET 0xc104
#define PWR_STABLE_OFFSET 0xc108
#define MTC_STABLE_OFFSET 0xc110
#define CLAMP_STABLE_OFFSET 0xc114
#define WAKEUP_STAT_OFFSET 0xc200
#define BLK_PWR_STAT_OFFSET 0xc204
#define BODY_BIAS_CON_OFFSET 0xc300
#define ION_SKEW_CON_OFFSET 0xc310
#define ION_SKEW_MON_OFFSET 0xc314
#define IOFF_SKEW_CON_OFFSET 0xc320
#define IOFF_SKEW_MON_OFFSET 0xc324
#define OTHERS_OFFSET 0xe000
#define OM_STAT_OFFSET 0xe100
#define MIE_CONTROL_OFFSET 0xe800
#define HDMI_CONTROL_OFFSET 0xe804
#define USB_PHY_CONTROL_OFFSET 0xe80c
#define DAC_CONTROL_OFFSET 0xe810
#define MIPI_DPHY_CONTROL_OFFSET 0xe814
#define ADC_CONTROL_OFFSET 0xe818
#define PS_HOLD_CONTROL_OFFSET 0xe81c
#define INFORM0_OFFSET 0xf000
#define INFORM1_OFFSET 0xf004
#define INFORM2_OFFSET 0xf008
#define INFORM3_OFFSET 0xf00c
#define INFORM4_OFFSET 0xf010
#define INFORM5_OFFSET 0xf014
#define INFORM6_OFFSET 0xf018
#define INFORM7_OFFSET 0xf01c
#define INF_REG0_OFFSET 0x00
#define INF_REG1_OFFSET 0x04
#define INF_REG2_OFFSET 0x08
#define INF_REG3_OFFSET 0x0c
#define INF_REG4_OFFSET 0x10
#define INF_REG5_OFFSET 0x14
#define INF_REG6_OFFSET 0x18
#define INF_REG7_OFFSET 0x1c
/*
* GPIO
*/
#define ELFIN_GPIO_BASE 0xE0200000
#define GPA0CON_OFFSET 0x000
#define GPA0DAT_OFFSET 0x004
#define GPA0PUD_OFFSET 0x008
#define GPA0DRV_SR_OFFSET 0x00C
#define GPA0CONPDN_OFFSET 0x010
#define GPA0PUDPDN_OFFSET 0x014
#define GPA1CON_OFFSET 0x020
#define GPA1DAT_OFFSET 0x024
#define GPA1PUD_OFFSET 0x028
#define GPA1DRV_SR_OFFSET 0x02C
#define GPA1CONPDN_OFFSET 0x030
#define GPA1PUDPDN_OFFSET 0x034
#define GPBCON_OFFSET 0x040
#define GPBDAT_OFFSET 0x044
#define GPBPUD_OFFSET 0x048
#define GPBDRV_SR_OFFSET 0x04C
#define GPBCONPDN_OFFSET 0x050
#define GPBPUDPDN_OFFSET 0x054
#define GPC0CON_OFFSET 0x060
#define GPC0DAT_OFFSET 0x064
#define GPC0PUD_OFFSET 0x068
#define GPC0DRV_SR_OFFSET 0x06C
#define GPC0CONPDN_OFFSET 0x070
#define GPC0PUDPDN_OFFSET 0x074
#define GPC1CON_OFFSET 0x080
#define GPC1DAT_OFFSET 0x084
#define GPC1PUD_OFFSET 0x088
#define GPC1DRV_SR_OFFSET 0x08C
#define GPC1CONPDN_OFFSET 0x090
#define GPC1PUDPDN_OFFSET 0x094
#define GPD0CON_OFFSET 0x0A0
#define GPD0DAT_OFFSET 0x0A4
#define GPD0PUD_OFFSET 0x0A8
#define GPD0DRV_SR_OFFSET 0x0AC
#define GPD0CONPDN_OFFSET 0x0B0
#define GPD0PUDPDN_OFFSET 0x0B4
#define GPD1CON_OFFSET 0x0C0
#define GPD1DAT_OFFSET 0x0C4
#define GPD1PUD_OFFSET 0x0C8
#define GPD1DRV_SR_OFFSET 0x0CC
#define GPD1CONPDN_OFFSET 0x0D0
#define GPD1PUDPDN_OFFSET 0x0D4
#define GPE0CON_OFFSET 0x0E0
#define GPE0DAT_OFFSET 0x0E4
#define GPE0PUD_OFFSET 0x0E8
#define GPE0DRV_SR_OFFSET 0x0EC
#define GPE0CONPDN_OFFSET 0x0F0
#define GPE0PUDPDN_OFFSET 0x0F4
#define GPE1CON_OFFSET 0x100
#define GPE1DAT_OFFSET 0x104
#define GPE1PUD_OFFSET 0x108
#define GPE1DRV_SR_OFFSET 0x10C
#define GPE1CONPDN_OFFSET 0x110
#define GPE1PUDPDN_OFFSET 0x114
#define GPF0CON_OFFSET 0x120
#define GPF0DAT_OFFSET 0x124
#define GPF0PUD_OFFSET 0x128
#define GPF0DRV_SR_OFFSET 0x12C
#define GPF0CONPDN_OFFSET 0x130
#define GPF0PUDPDN_OFFSET 0x134
#define GPF1CON_OFFSET 0x140
#define GPF1DAT_OFFSET 0x144
#define GPF1PUD_OFFSET 0x148
#define GPF1DRV_SR_OFFSET 0x14C
#define GPF1CONPDN_OFFSET 0x150
#define GPF1PUDPDN_OFFSET 0x154
#define GPF2CON_OFFSET 0x160
#define GPF2DAT_OFFSET 0x164
#define GPF2PUD_OFFSET 0x168
#define GPF2DRV_SR_OFFSET 0x16C
#define GPF2CONPDN_OFFSET 0x170
#define GPF2PUDPDN_OFFSET 0x174
#define GPF3CON_OFFSET 0x180
#define GPF3DAT_OFFSET 0x184
#define GPF3PUD_OFFSET 0x188
#define GPF3DRV_SR_OFFSET 0x18C
#define GPF3CONPDN_OFFSET 0x190
#define GPF3PUDPDN_OFFSET 0x194
#define GPG0CON_OFFSET 0x1A0
#define GPG0DAT_OFFSET 0x1A4
#define GPG0PUD_OFFSET 0x1A8
#define GPG0DRV_SR_OFFSET 0x1AC
#define GPG0CONPDN_OFFSET 0x1B0
#define GPG0PUDPDN_OFFSET 0x1B4
#define GPG1CON_OFFSET 0x1C0
#define GPG1DAT_OFFSET 0x1C4
#define GPG1PUD_OFFSET 0x1C8
#define GPG1DRV_SR_OFFSET 0x1CC
#define GPG1CONPDN_OFFSET 0x1D0
#define GPG1PUDPDN_OFFSET 0x1D4
#define GPG2CON_OFFSET 0x1E0
#define GPG2DAT_OFFSET 0x1E4
#define GPG2PUD_OFFSET 0x1E8
#define GPG2DRV_SR_OFFSET 0x1EC
#define GPG2CONPDN_OFFSET 0x1F0
#define GPG2PUDPDN_OFFSET 0x1F4
#define GPG3CON_OFFSET 0x200
#define GPG3DAT_OFFSET 0x204
#define GPG3PUD_OFFSET 0x208
#define GPG3DRV_SR_OFFSET 0x20C
#define GPG3CONPDN_OFFSET 0x210
#define GPG3PUDPDN_OFFSET 0x214
#define MP1_0DRV_SR_OFFSET 0x3CC
#define MP1_1DRV_SR_OFFSET 0x3EC
#define MP1_2DRV_SR_OFFSET 0x40C
#define MP1_3DRV_SR_OFFSET 0x42C
#define MP1_4DRV_SR_OFFSET 0x44C
#define MP1_5DRV_SR_OFFSET 0x46C
#define MP1_6DRV_SR_OFFSET 0x48C
#define MP1_7DRV_SR_OFFSET 0x4AC
#define MP1_8DRV_SR_OFFSET 0x4CC
#define MP2_0DRV_SR_OFFSET 0x4EC
#define MP2_1DRV_SR_OFFSET 0x50C
#define MP2_2DRV_SR_OFFSET 0x52C
#define MP2_3DRV_SR_OFFSET 0x54C
#define MP2_4DRV_SR_OFFSET 0x56C
#define MP2_5DRV_SR_OFFSET 0x58C
#define MP2_6DRV_SR_OFFSET 0x5AC
#define MP2_7DRV_SR_OFFSET 0x5CC
#define MP2_8DRV_SR_OFFSET 0x5EC
/* GPH0 */
#define GPH0CON_OFFSET 0xc00
#define GPH0DAT_OFFSET 0xc04
#define GPH0PUD_OFFSET 0xc08
#define GPH0DRV_OFFSET 0xc0c
/* GPH1 */
#define GPH1CON_OFFSET 0xc20
#define GPH1DAT_OFFSET 0xc24
#define GPH1PUD_OFFSET 0xc28
#define GPH1DRV_OFFSET 0xc2c
/* GPH2 */
#define GPH2CON_OFFSET 0xc40
#define GPH2DAT_OFFSET 0xc44
#define GPH2PUD_OFFSET 0xc48
#define GPH2DRV_OFFSET 0xc4c
/* GPH3 */
#define GPH3CON_OFFSET 0xc60
#define GPH3DAT_OFFSET 0xc64
#define GPH3PUD_OFFSET 0xc68
#define GPH3DRV_OFFSET 0xc6c
#define GPICON_OFFSET 0x220
#define GPIPUD_OFFSET 0x228
#define GPIDRV_OFFSET_SR 0x22C
#define GPIPUDPDN_OFFSET 0x234
#define GPJ0CON_OFFSET 0x240
#define GPJ0DAT_OFFSET 0x244
#define GPJ0PUD_OFFSET 0x248
#define GPJ0DRV_SR_OFFSET 0x24C
#define GPJ0CONPDN_OFFSET 0x250
#define GPJ0PUDPDN_OFFSET 0x254
#define GPJ1CON_OFFSET 0x260
#define GPJ1DAT_OFFSET 0x264
#define GPJ1PUD_OFFSET 0x268
#define GPJ1DRV_SR_OFFSET 0x26C
#define GPJ1CONPDN_OFFSET 0x270
#define GPJ1PUDPDN_OFFSET 0x274
#define GPJ2CON_OFFSET 0x280
#define GPJ2DAT_OFFSET 0x284
#define GPJ2PUD_OFFSET 0x288
#define GPJ2DRV_SR_OFFSET 0x28C
#define GPJ2CONPDN_OFFSET 0x290
#define GPJ2PUDPDN_OFFSET 0x294
#define GPJ3CON_OFFSET 0x2A0
#define GPJ3DAT_OFFSET 0x2A4
#define GPJ3PUD_OFFSET 0x2A8
#define GPJ3DRV_SR_OFFSET 0x2AC
#define GPJ3CONPDN_OFFSET 0x2B0
#define GPJ3PUDPDN_OFFSET 0x2B4
#define GPJ4CON_OFFSET 0x2C0
#define GPJ4DAT_OFFSET 0x2C4
#define GPJ4PUD_OFFSET 0x2C8
#define GPJ4DRV_SR_OFFSET 0x2CC
#define GPJ4CONPDN_OFFSET 0x2D0
#define GPJ4PUDPDN_OFFSET 0x2D4
/*
* Interrupt
*/
#define ELFIN_VIC0_BASE_ADDR (0xF2000000)
#define ELFIN_VIC1_BASE_ADDR (0xF2100000)
#define ELFIN_VIC2_BASE_ADDR (0xF2200000)
#define ELFIN_TZIC0_BASE_ADDR (0xF2800000)
#define ELFIN_TZIC1_BASE_ADDR (0xF2900000)
#define ELFIN_TZIC2_BASE_ADDR (0xF2A00000)
#define oINTMOD (0x0C) // VIC INT SELECT (IRQ or FIQ)
#define oINTUNMSK (0x10) // VIC INT EN (Unmask by writing 1)
#define oINTMSK (0x14) // VIC INT EN CLEAR (Mask by writing 1)
#define oINTSUBMSK (0x1C) // VIC SOFT INT CLEAR
#define oVECTADDR (0xF00) // VIC ADDRESS
/*
* Watchdog timer
*/
#define ELFIN_WATCHDOG_BASE 0xE2700000
#define WTCON_OFFSET 0x00
#define WTDAT_OFFSET 0x08
#define WTCNT_OFFSET 0x0C
#define WTCON_REG __REG(ELFIN_WATCHDOG_BASE+WTCON_OFFSET)
#define WTDAT_REG __REG(ELFIN_WATCHDOG_BASE+WTDAT_OFFSET)
#define WTCNT_REG __REG(ELFIN_WATCHDOG_BASE+WTCNT_OFFSET)
/*
* UART
*/
#define ELFIN_UART_BASE 0XE2900000
#define ELFIN_UART0_OFFSET 0x0000
#define ELFIN_UART1_OFFSET 0x0400
#define ELFIN_UART2_OFFSET 0x0800
#define ELFIN_UART3_OFFSET 0x0c00
#if defined(CONFIG_SERIAL0)
#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART0_OFFSET)
#elif defined(CONFIG_SERIAL1)
#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART1_OFFSET)
#elif defined(CONFIG_SERIAL2)
#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART2_OFFSET)
#elif defined(CONFIG_SERIAL3)
#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART3_OFFSET)
#else
#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART0_OFFSET)
#endif
#define ULCON_OFFSET 0x00
#define UCON_OFFSET 0x04
#define UFCON_OFFSET 0x08
#define UMCON_OFFSET 0x0C
#define UTRSTAT_OFFSET 0x10
#define UERSTAT_OFFSET 0x14
#define UFSTAT_OFFSET 0x18
#define UMSTAT_OFFSET 0x1C
#define UTXH_OFFSET 0x20
#define URXH_OFFSET 0x24
#define UBRDIV_OFFSET 0x28
#define UDIVSLOT_OFFSET 0x2C
#define UINTP_OFFSET 0x30
#define UINTSP_OFFSET 0x34
#define UINTM_OFFSET 0x38
#define UTRSTAT_TX_EMPTY BIT2
#define UTRSTAT_RX_READY BIT0
#define UART_ERR_MASK 0xF
/*
* PWM timer
*/
#define ELFIN_TIMER_BASE 0xE2500000
#define TCFG0_REG __REG(0xE2500000)
#define TCFG1_REG __REG(0xE2500004)
#define TCON_REG __REG(0xE2500008)
#define TCNTB0_REG __REG(0xE250000c)
#define TCMPB0_REG __REG(0xE2500010)
#define TCNTO0_REG __REG(0xE2500014)
#define TCNTB1_REG __REG(0xE2500018)
#define TCMPB1_REG __REG(0xE250001c)
#define TCNTO1_REG __REG(0xE2500020)
#define TCNTB2_REG __REG(0xE2500024)
#define TCMPB2_REG __REG(0xE2500028)
#define TCNTO2_REG __REG(0xE250002c)
#define TCNTB3_REG __REG(0xE2500030)
#define TCMPB3_REG __REG(0xE2500034)
#define TCNTO3_REG __REG(0xE2500038)
#define TCNTB4_REG __REG(0xE250003c)
#define TCNTO4_REG __REG(0xE2500040)
#define TINT_CSTAT __REG(0xE2500044)
/* Fields */
#define fTCFG0_DZONE Fld(8,16) /* the dead zone length (= timer 0) */
#define fTCFG0_PRE1 Fld(8,8) /* prescaler value for time 2,3,4 */
#define fTCFG0_PRE0 Fld(8,0) /* prescaler value for time 0,1 */
#define fTCFG1_MUX4 Fld(4,16)
/* bits */
#define TCFG0_DZONE(x) FInsrt((x), fTCFG0_DZONE)
#define TCFG0_PRE1(x) FInsrt((x), fTCFG0_PRE1)
#define TCFG0_PRE0(x) FInsrt((x), fTCFG0_PRE0)
#define TCON_4_AUTO (1 << 22) /* auto reload on/off for Timer 4 */
#define TCON_4_UPDATE (1 << 21) /* manual Update TCNTB4 */
#define TCON_4_ONOFF (1 << 20) /* 0: Stop, 1: start Timer 4 */
#define COUNT_4_ON (TCON_4_ONOFF*1)
#define COUNT_4_OFF (TCON_4_ONOFF*0)
#define TCON_3_AUTO (1 << 19) /* auto reload on/off for Timer 3 */
#define TIMER3_ATLOAD_ON (TCON_3_AUTO*1)
#define TIMER3_ATLAOD_OFF FClrBit(TCON, TCON_3_AUTO)
#define TCON_3_INVERT (1 << 18) /* 1: Inverter on for TOUT3 */
#define TIMER3_IVT_ON (TCON_3_INVERT*1)
#define TIMER3_IVT_OFF (FClrBit(TCON, TCON_3_INVERT))
#define TCON_3_MAN (1 << 17) /* manual Update TCNTB3,TCMPB3 */
#define TIMER3_MANUP (TCON_3_MAN*1)
#define TIMER3_NOP (FClrBit(TCON, TCON_3_MAN))
#define TCON_3_ONOFF (1 << 16) /* 0: Stop, 1: start Timer 3 */
#define TIMER3_ON (TCON_3_ONOFF*1)
#define TIMER3_OFF (FClrBit(TCON, TCON_3_ONOFF))
/* macros */
#define GET_PRESCALE_TIMER4(x) FExtr((x), fTCFG0_PRE1)
#define GET_DIVIDER_TIMER4(x) FExtr((x), fTCFG1_MUX4)
#define MP01CON_OFFSET 0x2E0
#define MP01DAT_OFFSET 0x2E4
#define MP01PUD_OFFSET 0x2E8
#define MP01DRV_SR_OFFSET 0x2EC
#define MP01CONPDN_OFFSET 0x2E0
#define MP01PUDPDN_OFFSET 0x2E4
#define MP02CON_OFFSET 0x300
#define MP02DAT_OFFSET 0x304
#define MP02PUD_OFFSET 0x308
#define MP02DRV_SR_OFFSET 0x30c
#define MP02CONPDN_OFFSET 0x310
#define MP02PUDPDN_OFFSET 0x314
#define MP03CON_OFFSET 0x320
#define MP03DAT_OFFSET 0x324
#define MP03PUD_OFFSET 0x328
#define MP03DRV_SR_OFFSET 0x32c
#define MP03CONPDN_OFFSET 0x330
#define MP03PUDPDN_OFFSET 0x334
#define MP06CON_OFFSET 0x380
#define MP06DAT_OFFSET 0x384
#define MP06PUD_OFFSET 0x388
#define MP06DRV_SR_OFFSET 0x38C
#define MP06CONPDN_OFFSET 0x390
#define MP06PUDPDN_OFFSET 0x394
#define MP07CON_OFFSET 0x3A0
#define MP07DAT_OFFSET 0x3A4
#define MP07PUD_OFFSET 0x3A8
#define MP07DRV_SR_OFFSET 0x3AC
#define MP07CONPDN_OFFSET 0x3B0
#define MP07PUDPDN_OFFSET 0x3B4
/*
* Nand flash controller
*/
#define ELFIN_NAND_BASE 0xB0E00000
#define ELFIN_NAND_ECC_BASE 0xB0E20000
#define NFCONF_OFFSET 0x00
#define NFCONT_OFFSET 0x04
#define NFCMMD_OFFSET 0x08
#define NFADDR_OFFSET 0x0c
#define NFDATA_OFFSET 0x10
#define NFMECCDATA0_OFFSET 0x14
#define NFMECCDATA1_OFFSET 0x18
#define NFSECCDATA0_OFFSET 0x1c
#define NFSBLK_OFFSET 0x20
#define NFEBLK_OFFSET 0x24
#define NFSTAT_OFFSET 0x28
#define NFESTAT0_OFFSET 0x2c
#define NFESTAT1_OFFSET 0x30
#define NFMECC0_OFFSET 0x34
#define NFMECC1_OFFSET 0x38
#define NFSECC_OFFSET 0x3c
#define NFMLCBITPT_OFFSET 0x40
#define NFECCCONF_OFFSET 0x000 // R/W ECC configuration register 0x0000_0000
#define NFECCCONT_OFFSET 0x020 // R/W ECC control register 0x0000_0000
#define NFECCSTAT_OFFSET 0x030 // R ECC status register 0x0000_0000
#define NFECCSECSTAT_OFFSET 0x040 // R ECC sector status register 0x0000_0000
#define NFECCPRGECC0_OFFSET 0x090 // R ECC parity code0 register for page program 0x0000_0000
#define NFECCPRGECC1_OFFSET 0x094 // R ECC parity code1 register for page program 0x0000_0000
#define NFECCPRGECC2_OFFSET 0x098 // R ECC parity code2 register for page program 0x0000_0000
#define NFECCPRGECC3_OFFSET 0x09C // R ECC parity code3 register for page program 0x0000_0000
#define NFECCPRGECC4_OFFSET 0x0A0 // R ECC parity code4 register for page program 0x0000_0000
#define NFECCPRGECC5_OFFSET 0x0A4 // R ECC parity code5 register for page program 0x0000_0000
#define NFECCPRGECC6_OFFSET 0x0A8 // R ECC parity code6 register for page program 0x0000_0000
#define NFECCERL0_OFFSET 0x0C0 // R ECC error byte location0 register 0x0000_0000
#define NFECCERL1_OFFSET 0x0C4 // R ECC error byte location1 register 0x0000_0000
#define NFECCERL2_OFFSET 0x0C8 // R ECC error byte location2 register 0x0000_0000
#define NFECCERL3_OFFSET 0x0CC // R ECC error byte location3 register 0x0000_0000
#define NFECCERL4_OFFSET 0x0D0 // R ECC error byte location4 register 0x0000_0000
#define NFECCERL5_OFFSET 0x0D4 // R ECC error byte location5 register 0x0000_0000
#define NFECCERL6_OFFSET 0x0D8 // R ECC error byte location6 register 0x0000_0000
#define NFECCERL7_OFFSET 0x0DC // R ECC error byte location7 register 0x0000_0000
#define NFECCERP0_OFFSET 0x0F0 // R ECC error bit pattern0 register 0x0000_0000
#define NFECCERP1_OFFSET 0x0F4 // R ECC error bit pattern1 register 0x0000_0000
#define NFECCERP2_OFFSET 0x0F8 // R ECC error bit pattern2 register 0x0000_0000
#define NFECCERP3_OFFSET 0x0FC // R ECC error bit pattern3 register 0x0000_0000
#define NFECCCONECC0_OFFSET 0x110 // R/W ECC parity conversion code0 register 0x0000_0000
#define NFECCCONECC1_OFFSET 0x114 // R/W ECC parity conversion code1 register 0x0000_0000
#define NFECCCONECC2_OFFSET 0x118 // R/W ECC parity conversion code2 register 0x0000_0000
#define NFECCCONECC3_OFFSET 0x11C // R/W ECC parity conversion code3 register 0x0000_0000
#define NFECCCONECC4_OFFSET 0x120 // R/W ECC parity conversion code4 register 0x0000_0000
#define NFECCCONECC5_OFFSET 0x124 // R/W ECC parity conversion code5 register 0x0000_0000
#define NFECCCONECC6_OFFSET 0x128 // R/W ECC parity conversion code6 register 0x0000_0000
#define NFCONF (ELFIN_NAND_BASE+NFCONF_OFFSET)
#define NFCONT (ELFIN_NAND_BASE+NFCONT_OFFSET)
#define NFCMMD (ELFIN_NAND_BASE+NFCMMD_OFFSET)
#define NFADDR (ELFIN_NAND_BASE+NFADDR_OFFSET)
#define NFDATA (ELFIN_NAND_BASE+NFDATA_OFFSET)
#define NFMECCDATA0 (ELFIN_NAND_BASE+NFMECCDATA0_OFFSET)
#define NFMECCDATA1 (ELFIN_NAND_BASE+NFMECCDATA1_OFFSET)
#define NFSECCDATA0 (ELFIN_NAND_BASE+NFSECCDATA0_OFFSET)
#define NFSBLK (ELFIN_NAND_BASE+NFSBLK_OFFSET)
#define NFEBLK (ELFIN_NAND_BASE+NFEBLK_OFFSET)
#define NFSTAT (ELFIN_NAND_BASE+NFSTAT_OFFSET)
#define NFESTAT0 (ELFIN_NAND_BASE+NFESTAT0_OFFSET)
#define NFESTAT1 (ELFIN_NAND_BASE+NFESTAT1_OFFSET)
#define NFMECC0 (ELFIN_NAND_BASE+NFMECC0_OFFSET)
#define NFMECC1 (ELFIN_NAND_BASE+NFMECC1_OFFSET)
#define NFSECC (ELFIN_NAND_BASE+NFSECC_OFFSET)
#define NFMLCBITPT (ELFIN_NAND_BASE+NFMLCBITPT_OFFSET)
#define NFECCCONF (ELFIN_NAND_ECC_BASE+NFECCCONF_OFFSET)
#define NFECCCONT (ELFIN_NAND_ECC_BASE+NFECCCONT_OFFSET)
#define NFECCSTAT (ELFIN_NAND_ECC_BASE+NFECCSTAT_OFFSET)
#define NFECCSECSTAT (ELFIN_NAND_ECC_BASE+NFECCSECSTAT_OFFSET)
#define NFECCPRGECC0 (ELFIN_NAND_ECC_BASE+NFECCPRGECC0_OFFSET)
#define NFECCPRGECC1 (ELFIN_NAND_ECC_BASE+NFECCPRGECC1_OFFSET)
#define NFECCPRGECC2 (ELFIN_NAND_ECC_BASE+NFECCPRGECC2_OFFSET)
#define NFECCPRGECC3 (ELFIN_NAND_ECC_BASE+NFECCPRGECC3_OFFSET)
#define NFECCPRGECC4 (ELFIN_NAND_ECC_BASE+NFECCPRGECC4_OFFSET)
#define NFECCPRGECC5 (ELFIN_NAND_ECC_BASE+NFECCPRGECC5_OFFSET)
#define NFECCPRGECC6 (ELFIN_NAND_ECC_BASE+NFECCPRGECC6_OFFSET)
#define NFECCERL0 (ELFIN_NAND_ECC_BASE+NFECCERL0_OFFSET)
#define NFECCERL1 (ELFIN_NAND_ECC_BASE+NFECCERL1_OFFSET)
#define NFECCERL2 (ELFIN_NAND_ECC_BASE+NFECCERL2_OFFSET)
#define NFECCERL3 (ELFIN_NAND_ECC_BASE+NFECCERL3_OFFSET)
#define NFECCERL4 (ELFIN_NAND_ECC_BASE+NFECCERL4_OFFSET)
#define NFECCERL5 (ELFIN_NAND_ECC_BASE+NFECCERL5_OFFSET)
#define NFECCERL6 (ELFIN_NAND_ECC_BASE+NFECCERL6_OFFSET)
#define NFECCERL7 (ELFIN_NAND_ECC_BASE+NFECCERL7_OFFSET)
#define NFECCERP0 (ELFIN_NAND_ECC_BASE+NFECCERP0_OFFSET)
#define NFECCERP1 (ELFIN_NAND_ECC_BASE+NFECCERP1_OFFSET)
#define NFECCERP2 (ELFIN_NAND_ECC_BASE+NFECCERP2_OFFSET)
#define NFECCERP3 (ELFIN_NAND_ECC_BASE+NFECCERP3_OFFSET)
#define NFECCCONECC0 (ELFIN_NAND_ECC_BASE+NFECCCONECC0_OFFSET)
#define NFECCCONECC1 (ELFIN_NAND_ECC_BASE+NFECCCONECC1_OFFSET)
#define NFECCCONECC2 (ELFIN_NAND_ECC_BASE+NFECCCONECC2_OFFSET)
#define NFECCCONECC3 (ELFIN_NAND_ECC_BASE+NFECCCONECC3_OFFSET)
#define NFECCCONECC4 (ELFIN_NAND_ECC_BASE+NFECCCONECC4_OFFSET)
#define NFECCCONECC5 (ELFIN_NAND_ECC_BASE+NFECCCONECC5_OFFSET)
#define NFECCCONECC6 (ELFIN_NAND_ECC_BASE+NFECCCONECC6_OFFSET)
#define NFCONF_REG __REG(ELFIN_NAND_BASE+NFCONF_OFFSET)
#define NFCONT_REG __REG(ELFIN_NAND_BASE+NFCONT_OFFSET)
#define NFCMD_REG __REG(ELFIN_NAND_BASE+NFCMMD_OFFSET)
#define NFADDR_REG __REG(ELFIN_NAND_BASE+NFADDR_OFFSET)
#define NFDATA_REG __REG(ELFIN_NAND_BASE+NFDATA_OFFSET)
#define NFDATA8_REG __REGb(ELFIN_NAND_BASE+NFDATA_OFFSET)
#define NFMECCDATA0_REG __REG(ELFIN_NAND_BASE+NFMECCDATA0_OFFSET)
#define NFMECCDATA1_REG __REG(ELFIN_NAND_BASE+NFMECCDATA1_OFFSET)
#define NFSECCDATA0_REG __REG(ELFIN_NAND_BASE+NFSECCDATA0_OFFSET)
#define NFSBLK_REG __REG(ELFIN_NAND_BASE+NFSBLK_OFFSET)
#define NFEBLK_REG __REG(ELFIN_NAND_BASE+NFEBLK_OFFSET)
#define NFSTAT_REG __REG(ELFIN_NAND_BASE+NFSTAT_OFFSET)
#define NFESTAT0_REG __REG(ELFIN_NAND_BASE+NFESTAT0_OFFSET)
#define NFESTAT1_REG __REG(ELFIN_NAND_BASE+NFESTAT1_OFFSET)
#define NFMECC0_REG __REG(ELFIN_NAND_BASE+NFMECC0_OFFSET)
#define NFMECC1_REG __REG(ELFIN_NAND_BASE+NFMECC1_OFFSET)
#define NFSECC_REG __REG(ELFIN_NAND_BASE+NFSECC_OFFSET)
#define NFMLCBITPT_REG __REG(ELFIN_NAND_BASE+NFMLCBITPT_OFFSET)
#define NFCONF_ECC_MLC (1<<24)
#define NFCONF_ECC_1BIT (0<<23)
#define NFCONF_ECC_4BIT (2<<23)
#define NFCONF_ECC_8BIT (1<<23)
#define NFCONT_ECC_ENC (1<<18)
#define NFCONT_WP (1<<16)
#define NFCONT_MECCLOCK (1<<7)
#define NFCONT_SECCLOCK (1<<6)
#define NFCONT_INITMECC (1<<5)
#define NFCONT_INITSECC (1<<4)
#define NFCONT_INITECC (NFCONT_INITMECC | NFCONT_INITSECC)
#define NFCONT_CS (1<<1)
#define NFSTAT_ECCENCDONE (1<<25)
#define NFSTAT_ECCDECDONE (1<<24)
#define NFSTAT_RnB (1<<0)
#define NFESTAT0_ECCBUSY (1<<31)
/* Access Controller (TZPC) */
#define TZPC_DECPROT0SET_OFFSET 0x804
#define TZPC_DECPROT1SET_OFFSET 0x810
#define TZPC_DECPROT2SET_OFFSET 0x81C
#define TZPC_DECPROT3SET_OFFSET 0x828
/*************************************************************
* OneNAND Controller
*************************************************************/
#define ELFIN_ONENAND_BASE 0xB0000000
#define ELFIN_ONENANDCON_BASE (ELFIN_ONENAND_BASE + 0x600000)
#define ONENAND_IF_CTRL_OFFSET 0x100
#define ONENAND_IF_CMD_OFFSET 0x104
#define ONENAND_IF_ASYNC_TIMING_CTRL_OFFSET 0x108
#define ONENAND_IF_STATUS_OFFSET 0x10C
#define DMA_SRC_ADDR_OFFSET 0x400
#define DMA_SRC_CFG_OFFSET 0x404
#define DMA_DST_ADDR_OFFSET 0x408
#define DMA_DST_CFG_OFFSET 0x40C
#define DMA_TRANS_SIZE_OFFSET 0x414
#define DMA_TRANS_CMD_OFFSET 0x418
#define DMA_TRANS_STATUS_OFFSET 0x41C
#define DMA_TRANS_DIR_OFFSET 0x420
#define SQC_SAO_OFFSET 0x600
#define SQC_CMD_OFFSET 0x608
#define SQC_STATUS_OFFSET 0x60C
#define SQC_CAO_OFFSET 0x610
#define SQC_REG_CTRL_OFFSET 0x614
#define SQC_REG_VAL_OFFSET 0x618
#define SQC_BRPAO0_OFFSET 0x620
#define SQC_BRPAO1_OFFSET 0x624
#define INTC_SQC_CLR_OFFSET 0x1000
#define INTC_DMA_CLR_OFFSET 0x1004
#define INTC_ONENAND_CLR_OFFSET 0x1008
#define INTC_SQC_MASK_OFFSET 0x1020
#define INTC_DMA_MASK_OFFSET 0x1024
#define INTC_ONENAND_MASK_OFFSET 0x1028
#define INTC_SQC_PEND_OFFSET 0x1040
#define INTC_DMA_PEND_OFFSET 0x1044
#define INTC_ONENAND_PEND_OFFSET 0x1048
#define INTC_SQC_STATUS_OFFSET 0x1060
#define INTC_DMA_STATUS_OFFSET 0x1064
#define INTC_ONENAND_STATUS_OFFSET 0x1068
/*
* Memory controller
*/
#define ELFIN_SROM_BASE 0xE8000000
#define SROM_BW_REG __REG(ELFIN_SROM_BASE+0x0)
#define SROM_BC0_REG __REG(ELFIN_SROM_BASE+0x4)
#define SROM_BC1_REG __REG(ELFIN_SROM_BASE+0x8)
#define SROM_BC2_REG __REG(ELFIN_SROM_BASE+0xC)
#define SROM_BC3_REG __REG(ELFIN_SROM_BASE+0x10)
#define SROM_BC4_REG __REG(ELFIN_SROM_BASE+0x14)
#define SROM_BC5_REG __REG(ELFIN_SROM_BASE+0x18)
/*
* SDRAM Controller
*/
#define APB_DMC_0_BASE 0xF0000000
#define APB_DMC_1_BASE 0xF1400000
#define ASYNC_MSYS_DMC0_BASE 0xF1E00000
#define DMC_CONCONTROL 0x00
#define DMC_MEMCONTROL 0x04
#define DMC_MEMCONFIG0 0x08
#define DMC_MEMCONFIG1 0x0C
#define DMC_DIRECTCMD 0x10
#define DMC_PRECHCONFIG 0x14
#define DMC_PHYCONTROL0 0x18
#define DMC_PHYCONTROL1 0x1C
#define DMC_RESERVED 0x20
#define DMC_PWRDNCONFIG 0x28
#define DMC_TIMINGAREF 0x30
#define DMC_TIMINGROW 0x34
#define DMC_TIMINGDATA 0x38
#define DMC_TIMINGPOWER 0x3C
#define DMC_PHYSTATUS 0x40
#define DMC_CHIP0STATUS 0x48
#define DMC_CHIP1STATUS 0x4C
#define DMC_AREFSTATUS 0x50
#define DMC_MRSTATUS 0x54
#define DMC_PHYTEST0 0x58
#define DMC_PHYTEST1 0x5C
#define DMC_QOSCONTROL0 0x60
#define DMC_QOSCONFIG0 0x64
#define DMC_QOSCONTROL1 0x68
#define DMC_QOSCONFIG1 0x6C
#define DMC_QOSCONTROL2 0x70
#define DMC_QOSCONFIG2 0x74
#define DMC_QOSCONTROL3 0x78
#define DMC_QOSCONFIG3 0x7C
#define DMC_QOSCONTROL4 0x80
#define DMC_QOSCONFIG4 0x84
#define DMC_QOSCONTROL5 0x88
#define DMC_QOSCONFIG5 0x8C
#define DMC_QOSCONTROL6 0x90
#define DMC_QOSCONFIG6 0x94
#define DMC_QOSCONTROL7 0x98
#define DMC_QOSCONFIG7 0x9C
#define DMC_QOSCONTROL8 0xA0
#define DMC_QOSCONFIG8 0xA4
#define DMC_QOSCONTROL9 0xA8
#define DMC_QOSCONFIG9 0xAC
#define DMC_QOSCONTROL10 0xB0
#define DMC_QOSCONFIG10 0xB4
#define DMC_QOSCONTROL11 0xB8
#define DMC_QOSCONFIG11 0xBC
#define DMC_QOSCONTROL12 0xC0
#define DMC_QOSCONFIG12 0xC4
#define DMC_QOSCONTROL13 0xC8
#define DMC_QOSCONFIG13 0xCC
#define DMC_QOSCONTROL14 0xD0
#define DMC_QOSCONFIG14 0xD4
#define DMC_QOSCONTROL15 0xD8
#define DMC_QOSCONFIG15 0xDC
/*
* Memory Chip direct command
*/
/****************************************************************
Definitions for memory configuration
Set memory configuration
active_chips = 1'b0 (1 chip)
qos_master_chip = 3'b000(ARID[3:0])
memory burst = 3'b010(burst 4)
stop_mem_clock = 1'b0(disable dynamical stop)
auto_power_down = 1'b0(disable auto power-down mode)
power_down_prd = 6'b00_0000(0 cycle for auto power-down)
ap_bit = 1'b0 (bit position of auto-precharge is 10)
row_bits = 3'b010(# row address 13)
column_bits = 3'b010(# column address 10 )
Set user configuration
2'b10=SDRAM/mSDRAM, 2'b11=DDR, 2'b01=mDDR
Set chip select for chip [n]
row bank control, bank address 0x3000_0000 ~ 0x37ff_ffff
CHIP_[n]_CFG=0x30F8, 30: ADDR[31:24], F8: Mask[31:24]
******************************************************************/
#define INF_REG_BASE 0xE010F000
#define INF_REG0_REG __REG(INF_REG_BASE+INF_REG0_OFFSET)
#define INF_REG1_REG __REG(INF_REG_BASE+INF_REG1_OFFSET)
#define INF_REG2_REG __REG(INF_REG_BASE+INF_REG2_OFFSET)
#define INF_REG3_REG __REG(INF_REG_BASE+INF_REG3_OFFSET)
#define INF_REG4_REG __REG(INF_REG_BASE+INF_REG4_OFFSET)
#define INF_REG5_REG __REG(INF_REG_BASE+INF_REG5_OFFSET)
#define INF_REG6_REG __REG(INF_REG_BASE+INF_REG6_OFFSET)
#define INF_REG7_REG __REG(INF_REG_BASE+INF_REG7_OFFSET)
#define NFCONF_VAL (7<<12)|(7<<8)|(7<<4)|(0<<3)|(0<<2)|(1<<1)|(0<<0)
#define NFCONT_VAL (0x1<<23)|(0x1<<22)|(0<<18)|(0<<17)|(0<<16)|(0<<10)|(0<<9)|(0<<8)|(0<<7)|(0<<6)|(0x2<<1)|(1<<0)
#define MP03CON_VAL (1<<29)|(1<<25)|(1<<21)|(1<<17)|(1<<13)|(1<<9)|(1<<5)|(1<<1)
#define ELFIN_TZPC0_BASE 0xF1500000
#define ELFIN_TZPC1_BASE 0xFAD00000
#define ELFIN_TZPC2_BASE 0xE0600000
#define ELFIN_TZPC3_BASE 0xE1C00000load_sd_bl2_2_ddr.c
#define CHANNEL 2
#define SD_START_BLOCK 45
#define SD_BLOCK_COUNT 1024
#define DDR_START_ADDR 0x23E00000
#define WITH_INIT 0
typedef unsigned int bool;
typedef bool(*copy_sdmmc_to_mem)(int, unsigned int, unsigned short, unsigned int*, bool);
typedef void (*bl2_type)();
void copy_bl2_2_ddr()
{
//the func is copy bl2 to ddr
//0xD0037F98 is the address of cpoy func
//define func
copy_sdmmc_to_mem copy = (copy_sdmmc_to_mem) (*((unsigned int *)0xD0037F98));
//use func
copy(CHANNEL, SD_START_BLOCK, SD_BLOCK_COUNT, (unsigned int *)DDR_START_ADDR,WITH_INIT);
//jump ddr,work bl2
bl2_type bl2 = (bl2_type) DDR_START_ADDR;
bl2();
}link.lds
SECTIONS
{
. = 0xd0020010;
.text :
{
start.o
* (.text)
}
.data :
{
* (.data)
}
.bss :
{
* (.bss)
}
}Makefile
CC = arm-linux-gcc
LD = arm-linux-ld
OBJCOPY = arm-linux-objcopy
OBJDUMP = arm-linux-objdump
INCDIR := $(shell pwd)
#预处理器的flag，flag就是编译器可选的选项
CPPFLAGS := -nostdlib -nostdinc -I$(INCDIR)/include
#C编译器的flag
CFLAGS := -Wall -O2 -fno-builtin
export CC LD OBJCOPY OBJDUMP CPPFLAGS CFLAGS
objs := start.o load_sd_bl2_2_ddr.o sdram_init.o
bl1.bin:$(objs)
$(LD) -Tlink.lds -o bl1.elf $^
$(OBJCOPY) -O binary bl1.elf bl1.bin
$(OBJDUMP) -D bl1.elf > bl1.dis
gcc mkv210.c -o mkv210
./mkv210 bl1.bin sd1.bin
%.o:%.S
$(CC) $(CPPFLAGS) $(CFLAGS) -o $@ $< -c
%.o:%.c
$(CC) $(CPPFLAGS) $(CFLAGS) -o $@ $< -c
clean:
rm *.o *.elf *.bin *.dis mkv210 -fbl2:
start.S
#define IRQ_STACK 0xd0037f80
.global _start
.global IRQ_handler
_start:
//clear bss
ldr r0,=bss_start
ldr r1,=bss_end
mov r2,#0
cmp r0,r1
beq run_to_func
clear_bss:
str r2,[r0],#4
cmp r1,r0
bne clear_bss
run_to_func:
ldr pc,=main
b .
//all interrupt process:Protect the scene + mian iqr process + return scene
IRQ_handler:
//init IRQ_STACK
ldr sp, =IRQ_STACK
//protect lr
sub lr, lr, #4
//protect r0--r12 that in irq stack
stmfd sp!, {r0-r12, lr}
//mian iqr process
bl irq_handler
//return scene
ldmfd sp!, {r0-r12, pc}^mian.c
#include "stdio.h"
#include "string.h"
#include "io.h"
#include "cmd.h"
#include "global_param.h"
#include "interrupt.h"
#include "uart_printf.h"
#define CMD_MAX_LENGTH 128
int isgo = 0;
char cmd[CMD_MAX_LENGTH];
unsigned int argvs_num;
void do_bootdealy()
{
while ((!isgo) && (!judge_key_press()));
disable_num(NUM_WDT);
}
void shell_cmd()
{
memset(cmd,'\0',sizeof(cmd));
gets(cmd);
argvs_num = split_cmd(cmd);
cmd_judge(argvs_num);
printf("root#");
}
int main()
{
init_device();
do_bootdealy();
while(1)
{
shell_cmd();
}
return 0;
}global_param.h
#define NUM_WDT (27)
extern int isgo;uart_printf.h
void init_uart();
void uart_send(char data);
char uart_get();
int judge_key_press();uart_printf.c
#define GPA0CON 0xE0200000
#define ULCON0 0xE2900000
#define UCON0 0xE2900004
#define UFCON0 0xE2900008
#define UMCON0 0xE290000C
#define UTRSTAT0 0xE2900010
#define UTXH0 0xE2900020
#define URXH0 0xE2900024
#define UBRDIV0 0xE2900028
#define UDIVSLOT0 0xE290002C
#define rGPA0CON (*(volatile unsigned int *)GPA0CON)
#define rULCON0 (*(volatile unsigned int *)ULCON0)
#define rUCON0 (*(volatile unsigned int *)UCON0)
#define rUFCON0 (*(volatile unsigned int *)UFCON0)
#define rUMCON0 (*(volatile unsigned int *)UMCON0)
#define rUTRSTAT0 (*(volatile unsigned int *)UTRSTAT0)
#define rUTXH0 (*(volatile unsigned int *)UTXH0)
#define rURXH0 (*(volatile unsigned int *)URXH0)
#define rUBRDIV0 (*(volatile unsigned int *)UBRDIV0)
#define rUDIVSLOT0 (*(volatile unsigned int *)UDIVSLOT0)
//init uart
void init_uart()
{
//set gpio as uart(rx,tx)
rGPA0CON &= ~(0xff);
rGPA0CON |= ((1<<1)|(1<<5));
//set uart base configure(mode)
rULCON0 = 0x3;
rUCON0 = 0x5;
rUMCON0 = 0;
rUFCON0 = 0;
//set uart baud
//DIV_VAL = (PCLK / (bps x 16))-1
//(66000000 /(115200 * 16)) -1 = 34.8
rUBRDIV0 = 34;
//set uart baud calibration
//0.8 * 16 = 13,check 210 table
rUDIVSLOT0 = 0xdfdd;
}
//send data
void putc(char data)
{
if (data == '\n')
{
while (!(rUTRSTAT0 & (1<<1)));
rUTXH0 = '\r';
}
while (!(rUTRSTAT0 & (1<<1)));
rUTXH0 = data;
}
//receive data
char getc()
{
while (!(rUTRSTAT0 & (1<<0)));
return (rURXH0 & 0xff);
}
//send data
void uart_send(char data)
{
while (!(rUTRSTAT0 & (1<<1)));
rUTXH0 = data;
}
//receive data
char uart_get()
{
while (!(rUTRSTAT0 & (1<<0)));
return (rURXH0 & 0xff);
}
int judge_key_press()
{
if ((rUTRSTAT0 & (1<<0)))
return 1;
else
return 0;
}io.h
void putchar(char c);
void puts(const char *p);
char getchar(void);
char *gets(char *p);io.c
#include "uart_printf.h"
void putchar(char c)
{
if (c == '\n')
uart_send('\r');
uart_send(c);
}
void puts(const char *p)
{
while (*p != '\0')
{
putchar(*p);
p++;
}
}
char getchar(void)
{
char c;
c = uart_get();
if (c == '\r')
{
return '\n';
}
return c;
}
char *gets(char *p)
{
char *p1 = p;
char ch;
while ((ch = getchar()) != '\n')
{
if (ch != '\b')
{
putchar(ch);
*p++ = ch;
}
else
{
if (p > p1)
{
putchar('\b');
putchar(' ');
putchar('\b');
p--;
*p = '\0';
}
}
}
*p = '\0';
putchar('\n');
return p1;
}cmd.h
void init_device();
unsigned int split_cmd(const char *cmd_string);
void cmd_judge(unsigned int argvs_num);cmd.c
#include "stdio.h"
#include "string.h"
#include "led.h"
#include "adc.h"
#include "lcd.h"
#include "uart_printf.h"
#include "buzzer.h"
#include "interrupt.h"
#include "env.h"
#define CDM_PART_LENGTH 24
#define CDM_PART_COUNT 8
#define BLACK 0x000000
#define WHITE 0xFFFFFF
char sp_cmd[CDM_PART_COUNT][CDM_PART_LENGTH];
static int string_2_int(char *str)
{
int num = 0;
while(*str != '\0')
{
num = num * 10 + (*str - '0');
str++;
}
return num;
}
void init_device()
{
init_uart();
init_led();
init_adc();
lcd_init();
init_background(WHITE);
pwn_buzzer_timer_init();
interrupt_init();
env_init();
}
unsigned int split_cmd(const char *cmd_string)
{
unsigned int m = 0;
unsigned int n = 0;
memset(sp_cmd,'\0',sizeof(sp_cmd));
while(*cmd_string != '\0')
{
if(*cmd_string != ' ')
{
sp_cmd[m][n] = *cmd_string;
n++;
}
else
{
sp_cmd[m][n] = '\0';
n = 0;
m++;
}
cmd_string++;
}
return m;
}
void cmd_judge(unsigned int argvs_num)
{
if(!(strcmp(sp_cmd[0],"led")))
{
if(!(strcmp(sp_cmd[1],"on")))
{
led_on();
}
else if(!(strcmp(sp_cmd[1],"off")))
{
led_off();
}
else
{
printf("command error\r\n");
printf("input:led on|off\r\n");
}
}
else if(!(strcmp(sp_cmd[0],"env")))
{
if(!(strcmp(sp_cmd[1],"print")))
{
print_env();
}
else if(!(strcmp(sp_cmd[1],"set")))
{
if(argvs_num != 3)
{
printf("command error\r\n");
printf("input:env set name val\r\n");
}
else
{
set_env(sp_cmd[2],sp_cmd[3]);
}
}
else if(!(strcmp(sp_cmd[1],"delete")))
{
if(argvs_num != 2)
{
printf("command error\r\n");
printf("input:env delete name\r\n");
}
else
{
delete_env(sp_cmd[2]);
}
}
else
{
printf("command error\r\n");
printf("input:env print\r\n");
printf(" env delete name\r\n");
printf(" env set name val\r\n");
}
}
else if(!(strcmp(sp_cmd[0],"adc")))
{
if(!(strcmp(sp_cmd[1],"sample")))
{
read_adc_data();
}
else
{
printf("command error\r\n");
printf("adc sample\r\n");
}
}
else if(!(strcmp(sp_cmd[0],"buzzer")))
{
if(!(strcmp(sp_cmd[1],"on")))
{
buzzer_open();
}
else if(!(strcmp(sp_cmd[1],"off")))
{
buzzer_close();
}
else
{
printf("command error\r\n");
printf("buzzer on|off\r\n");
}
}
else if(!(strcmp(sp_cmd[0],"lcd")))
{
if(!(strcmp(sp_cmd[1],"line")))
{
if(argvs_num != 5)
{
printf("command error\r\n");
printf("lcd line x1 y1 x2 y2\r\n");
}
else
{
init_background(WHITE);
lcd_draw_line(string_2_int(sp_cmd[2]),string_2_int(sp_cmd[3]),string_2_int(sp_cmd[4]),string_2_int(sp_cmd[5]),BLACK);
}
}
else if(!(strcmp(sp_cmd[1],"circle")))
{
if(argvs_num != 4)
{
printf("command error\r\n");
printf("lcd circle centerX1 centerY1 radius\r\n");
}
else
{
init_background(WHITE);
lcd_draw_circle(string_2_int(sp_cmd[2]),string_2_int(sp_cmd[3]),string_2_int(sp_cmd[4]),BLACK);
}
}
else if(!(strcmp(sp_cmd[1],"string")))
{
if(argvs_num < 2)
{
printf("command error\r\n");
printf("lcd string string\r\n");
}
else
{
unsigned int i;
char str[100] = {'\0'};
for(i = 2; i<= argvs_num;i++)
{
strcat(str,sp_cmd[i]);
strcat(str," ");
}
init_background(WHITE);
lcd_draw_string(0,0,BLACK,str);
}
}
else
{
printf("command error\r\n");
printf("input:lcd line|circle|string args\r\n");
printf(" lcd line x1 y1 x2 y2\r\n");
printf(" lcd circle centerX1 centerY1\r\n");
printf(" lcd string string\r\n");
}
}
else
{
printf("input:led on|off\r\n");
printf(" adc sample\r\n");
printf(" lcd line|circle|string args\r\n");
printf(" lcd line x1 y1 x2 y2\r\n");
printf(" lcd circle centerX1 centerY1 radius\r\n");
printf(" lcd string string\r\n");
printf(" buzzer on|off\r\n");
printf(" env print|delete|set\r\n");
printf(" env print\r\n");
printf(" env delete name\r\n");
printf(" env set name val\r\n");
}
}led.h
void init_led();
void led_on();
void led_off();led.c
#define GPJ0CON 0xE0200240
#define GPJ0DAT 0xE0200244
#define rGPJ0CON *((volatile unsigned int *) GPJ0CON)
#define rGPJ0DAT *((volatile unsigned int *) GPJ0DAT)
void init_led()
{
//set jpio output
rGPJ0CON = 0x11111111;
}
void led_on()
{
rGPJ0DAT = ((0<<3)|(0<<4)|(0<<5));
}
void led_off()
{
rGPJ0DAT = ((1<<3)|(1<<4)|(1<<5));
}adc.h
void init_adc();
void read_adc_data();adc.c
#include "stdio.h"
#define TSADCCON0 0xE1700000
#define TSDATX0 0xE170000C
#define TSDATY0 0xE1700010
#define ADCMUX 0xE170001C
#define rTSADCCON0 (*(volatile unsigned int *)TSADCCON0)
#define rTSDATX0 (*(volatile unsigned int *)TSDATX0)
#define rTSDATY0 (*(volatile unsigned int *)TSDATY0)
#define rADCMUX (*(volatile unsigned int *)ADCMUX)
void init_adc()
{
//set adc is 10 bit
rTSADCCON0 |= (1<<16);
//set adc enable prescaler
rTSADCCON0 |= (1<<14);
//set adc prescaler value,value = 66 / (65 + 1) = 1Mhz
rTSADCCON0 &= ~(0xff<<6);
rTSADCCON0 |= (65<<6);
//set adc mode(normal)
rTSADCCON0 &= ~(1<<2);
//close when start adc is read only
rTSADCCON0 &= ~(1<<1);
//select adc channel 0
rADCMUX &= ~(0xf);
}
void read_adc_data()
{
volatile unsigned int x_value = 0;
//start adc
rTSADCCON0 |= (1<<0);
//judge adc adc covert status(end or ing)
while(!(rTSADCCON0 & (1<<15)));
//read adc data
x_value = rTSDATX0;
printf("read adc data : x : %d\r\n",(x_value & 0xfff));
}buzzer.h
void pwn_buzzer_timer_init();
void buzzer_open();
void buzzer_close();buzzer.c
#define GPD0CON 0xE02000A0
#define TCFG0 0xE2500000
#define TCFG1 0xE2500004
#define TCON 0xE2500008
#define TCNTB2 0xE2500024
#define TCMPB2 0xE2500028
#define rGPD0CON (*(volatile unsigned int *) GPD0CON)
#define rTCFG0 (*(volatile unsigned int *) TCFG0)
#define rTCFG1 (*(volatile unsigned int *) TCFG1)
#define rTCON (*(volatile unsigned int *) TCON)
#define rTCNTB0 (*(volatile unsigned int *) TCNTB2)
#define rTCMPB2 (*(volatile unsigned int *) TCMPB2)
void pwn_buzzer_timer_init()
{
//set gpio as buzzer
rGPD0CON &= ~(0x0f << 8);
rGPD0CON |= (2 << 8);
//set Prescaler as 65,real Prescaleris 66,Prescaler is 66Mhz /66 = 1Mhz
rTCFG0 &= ~(0xff<<8);
rTCFG0 = (65<<8);
//set div ,set div is 2 that mean 1/2,so 1Mhz /2 = 500000hz = 2us
rTCFG1 &= ~(0x0f<<8);
rTCFG1 = (1<<8);
//set TCON,set Auto Reload open
rTCON = (1<<15);
//set TCNTB0,set the count of cycle
//rTCNTB0 = time you need / set div
//ex: 1ms / 2us = 500
rTCNTB0 = 500;
//set TCMPB2,set the rate of duty,mean the rate of high and low level on all cycle
rTCMPB2 = 250;
//set TCON,when firstly open timer that you Manual Refresh TCNTB0 to TCNT
rTCON |= (1<<13);
//after Manual Refresh,close Manual Refresh,then always Auto Reload
rTCON &= ~(1<<13);
}
void buzzer_open()
{
//set TCON,open timer
rTCON |= (1<<12);
}
void buzzer_close()
{
//set TCON,open timer
rTCON &= ~(1<<12);
}interrupt.h
void interrupt_init();
void disable_num(unsigned long intnum);interrupt.c
#include "stdio.h"
#include "uart_printf.h"
#include "global_param.h"
//watchDog interrupt register
#define WTCON 0xE2700000
#define WTDAT 0xE2700004
#define WTCNT 0xE2700008
#define WTCLRINT 0xE270000C
#define rWTCON *((volatile unsigned int *) WTCON)
#define rWTDAT *((volatile unsigned int *) WTDAT)
#define rWTCNT *((volatile unsigned int *) WTCNT)
#define rWTCLRINT *((volatile unsigned int *) WTCLRINT)
//inner interrupt register
//VIC base address
#define VIC0_BASE 0xF2000000
#define VIC1_BASE 0xF2100000
#define VIC2_BASE 0xF2200000
#define VIC3_BASE 0xF2300000
//VIC0 register
#define rVIC0IRQSTATUS (*(volatile unsigned int *)(VIC0_BASE + 0x0000))
#define rVIC0FIQSTATUS (*(volatile unsigned int *)(VIC0_BASE + 0x0004))
#define rVIC0INTSELECT (*(volatile unsigned int *)(VIC0_BASE + 0x000C))
#define rVIC0INTENABLE (*(volatile unsigned int *)(VIC0_BASE + 0x0010))
#define rVIC0INTENCLEAR (*(volatile unsigned int *)(VIC0_BASE + 0x0014))
#define rVIC0VECTADDR (VIC0_BASE + 0x100)
#define rVIC0ADDRESS (*(volatile unsigned int *)(VIC0_BASE + 0x0F00))
//VIC1 register
#define rVIC1IRQSTATUS (*(volatile unsigned int *)(VIC1_BASE + 0x0000))
#define rVIC1FIQSTATUS (*(volatile unsigned int *)(VIC1_BASE + 0x0004))
#define rVIC1INTSELECT (*(volatile unsigned int *)(VIC1_BASE + 0x000C))
#define rVIC1INTENABLE (*(volatile unsigned int *)(VIC1_BASE + 0x0010))
#define rVIC1INTENCLEAR (*(volatile unsigned int *)(VIC1_BASE + 0x0014))
#define rVIC1VECTADDR (VIC1_BASE + 0x100)
#define rVIC1ADDRESS (*(volatile unsigned int *)(VIC1_BASE + 0x0F00))
//VIC2 register
#define rVIC2IRQSTATUS (*(volatile unsigned int *)(VIC2_BASE + 0x0000))
#define rVIC2FIQSTATUS (*(volatile unsigned int *)(VIC2_BASE + 0x0004))
#define rVIC2INTSELECT (*(volatile unsigned int *)(VIC2_BASE + 0x000C))
#define rVIC2INTENABLE (*(volatile unsigned int *)(VIC2_BASE + 0x0010))
#define rVIC2INTENCLEAR (*(volatile unsigned int *)(VIC2_BASE + 0x0014))
#define rVIC2VECTADDR (VIC2_BASE + 0x100)
#define rVIC2ADDRESS (*(volatile unsigned int *)(VIC2_BASE + 0x0F00))
//VIC3 register
#define rVIC3IRQSTATUS (*(volatile unsigned int *)(VIC3_BASE + 0x0000))
#define rVIC3FIQSTATUS (*(volatile unsigned int *)(VIC3_BASE + 0x0004))
#define rVIC3INTSELECT (*(volatile unsigned int *)(VIC3_BASE + 0x000C))
#define rVIC3INTENABLE (*(volatile unsigned int *)(VIC3_BASE + 0x0010))
#define rVIC3INTENCLEAR (*(volatile unsigned int *)(VIC3_BASE + 0x0014))
#define rVIC3VECTADDR (VIC3_BASE + 0x100)
#define rVIC3ADDRESS (*(volatile unsigned int *)(VIC3_BASE + 0x0F00))
//interrupt vector table
#define vector_table_base 0xD0037400
#define reset_vector (vector_table_base + 0x00)
#define undef_vector (vector_table_base + 0x04)
#define sotf_interrupt_vector (vector_table_base + 0x08)
#define prefetch_vector (vector_table_base + 0x0C)
#define data_vector (vector_table_base + 0x10)
#define irq_vector (vector_table_base + 0x18)
#define fiq_vector (vector_table_base + 0x1C)
#define r_reset_vector (*(volatile unsigned int *) reset_vector)
#define r_undef_vector (*(volatile unsigned int *) undef_vector)
#define r_sotf_interrupt_vector (*(volatile unsigned int *) sotf_interrupt_vector)
#define r_prefetch_vector (*(volatile unsigned int *) prefetch_vector)
#define r_data_vector (*(volatile unsigned int *) data_vector)
#define r_irq_vector (*(volatile unsigned int *) irq_vector)
#define r_fiq_vector (*(volatile unsigned int *) fiq_vector)
//interrupt number
#define NUM_TIMER0 (21)
#define NUM_TIMER1 (22)
#define NUM_TIMER2 (23)
#define NUM_TIMER3 (24)
#define NUM_TIMER4 (25)
#define NUM_SYSTIMER (26)
#define NUM_WDT (27)
#define NUM_RTC_ALARM (28)
#define NUM_RTC_TICK (29)
//wdt interrupt func
void wdt_interrupt()
{
//set WTCON,set Prescaler,Prescaler is set value + 1
//Prescaler = 65 + 1 = 66,66Mhz / 66 = 1Mhz = 1000000hz
rWTCON &= ~(0xff << 8);
rWTCON |= (65<<8);
//set div is 128,t = 1/(1000000hz /128) = 1.28us
rWTCON &= ~(3 << 3);
rWTCON |= (3<<3);
//set WTCON,open interrupt and close reset
rWTCON |= (1<<2);
rWTCON &= ~(1);
//set WTDAT,set set the time form firstly open timer to count open(WTCNT)
rWTDAT = 7812;
rWTCNT = 7812;
//open wdt
rWTCON |= (1<<5);
}
//outer interrupt key func
unsigned int bootdealy = 9;
static void dealy_time()
{
volatile unsigned int i = 1000000;
while(i--);
}
static void isr_wdt()
{
if(bootdealy > 0)
{
printf("%d",bootdealy-1);
bootdealy--;
dealy_time();
putchar('\b');
}
else
{
putchar(' ');
isgo = 1;
}
//clear VIC0ADDR,clear using interrupt process
rVIC0ADDRESS = 0;
rVIC1ADDRESS = 0;
rVIC2ADDRESS = 0;
rVIC3ADDRESS = 0;
rWTCLRINT = 1;
}
//inner interrupt func
static void reset_func()
{
printf("reset\n");
}
static void undef_func()
{
printf("undef\n");
}
static void sotf_interrupt_func()
{
printf("sotf_intrrupt\n");
}
static void prefetch_func()
{
printf("prefetch\n");
}
static void data_func()
{
printf("data\n");
}
static void fiq_func()
{
printf("irq\n");
}
void IRQ_handler();
static void bind_isr_VICnINTENCLEAR(unsigned long num,void (*handler)())
{
if(num <32)
{
*((volatile unsigned int *)(rVIC0VECTADDR + 4 * (num))) = (unsigned)handler;
}
else if(num < 64)
{
*((volatile unsigned int *)(rVIC0VECTADDR + 4 * (num-32))) = (unsigned)handler;
}
else if(num < 96)
{
*((volatile unsigned int *)(rVIC0VECTADDR + 4 * (num-64))) = (unsigned)handler;
}
else
{
*((volatile unsigned int *)(rVIC0VECTADDR + 4 * (num-96))) = (unsigned)handler;
}
}
void disable_num(unsigned long intnum)
{
unsigned long temp;
if(intnum<32)
{
temp = rVIC0INTENCLEAR;
temp |= (1<lcd .h
void lcd_init();
void init_background(unsigned int color);
void lcd_draw_line(unsigned int x1, unsigned int y1, unsigned int x2, unsigned int y2, unsigned int color);
void lcd_draw_circle(unsigned int centerX, unsigned int centerY, unsigned int radius, unsigned int color);
void lcd_draw_string(unsigned int x, unsigned int y, unsigned int color, unsigned char *str);ascii.h
#ifndef __ASCII_H__
#define __ASCII_H__
//以下字模与ASCII对应是，只要将 'A'-0x20就可以得到A的字模了
//高8*5宽 ASCII码
//提取方式:纵向取模,字节倒序
//以下是8*16的
//高是16
//横向扫描
const unsigned char ascii_8_16[95][16]=
{
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*" ",0*/
{0x00,0x00,0x00,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x00,0x00,0x18,0x18,0x00,0x00},/*"!",1*/
{0x00,0x48,0x6C,0x24,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*""",2*/
{0x00,0x00,0x00,0x24,0x24,0x24,0x7F,0x12,0x12,0x12,0x7F,0x12,0x12,0x12,0x00,0x00},/*"#",3*/
{0x00,0x00,0x08,0x1C,0x2A,0x2A,0x0A,0x0C,0x18,0x28,0x28,0x2A,0x2A,0x1C,0x08,0x08},/*"{1}quot;,4*/
{0x00,0x00,0x00,0x22,0x25,0x15,0x15,0x15,0x2A,0x58,0x54,0x54,0x54,0x22,0x00,0x00},/*"%",5*/
{0x00,0x00,0x00,0x0C,0x12,0x12,0x12,0x0A,0x76,0x25,0x29,0x11,0x91,0x6E,0x00,0x00},/*"&",6*/
{0x00,0x06,0x06,0x04,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"'",7*/
{0x00,0x40,0x20,0x10,0x10,0x08,0x08,0x08,0x08,0x08,0x08,0x10,0x10,0x20,0x40,0x00},/*"(",8*/
{0x00,0x02,0x04,0x08,0x08,0x10,0x10,0x10,0x10,0x10,0x10,0x08,0x08,0x04,0x02,0x00},/*")",9*/
{0x00,0x00,0x00,0x00,0x08,0x08,0x6B,0x1C,0x1C,0x6B,0x08,0x08,0x00,0x00,0x00,0x00},/*"*",10*/
{0x00,0x00,0x00,0x00,0x08,0x08,0x08,0x08,0x7F,0x08,0x08,0x08,0x08,0x00,0x00,0x00},/*"+",11*/
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x06,0x04,0x03},/*",",12*/
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"-",13*/
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x06,0x00,0x00},/*".",14*/
{0x00,0x00,0x80,0x40,0x40,0x20,0x20,0x10,0x10,0x08,0x08,0x04,0x04,0x02,0x02,0x00},/*"/",15*/
{0x00,0x00,0x00,0x18,0x24,0x42,0x42,0x42,0x42,0x42,0x42,0x42,0x24,0x18,0x00,0x00},/*"0",16*/
{0x00,0x00,0x00,0x08,0x0E,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x3E,0x00,0x00},/*"1",17*/
{0x00,0x00,0x00,0x3C,0x42,0x42,0x42,0x20,0x20,0x10,0x08,0x04,0x42,0x7E,0x00,0x00},/*"2",18*/
{0x00,0x00,0x00,0x3C,0x42,0x42,0x20,0x18,0x20,0x40,0x40,0x42,0x22,0x1C,0x00,0x00},/*"3",19*/
{0x00,0x00,0x00,0x20,0x30,0x28,0x24,0x24,0x22,0x22,0x7E,0x20,0x20,0x78,0x00,0x00},/*"4",20*/
{0x00,0x00,0x00,0x7E,0x02,0x02,0x02,0x1A,0x26,0x40,0x40,0x42,0x22,0x1C,0x00,0x00},/*"5",21*/
{0x00,0x00,0x00,0x38,0x24,0x02,0x02,0x1A,0x26,0x42,0x42,0x42,0x24,0x18,0x00,0x00},/*"6",22*/
{0x00,0x00,0x00,0x7E,0x22,0x22,0x10,0x10,0x08,0x08,0x08,0x08,0x08,0x08,0x00,0x00},/*"7",23*/
{0x00,0x00,0x00,0x3C,0x42,0x42,0x42,0x24,0x18,0x24,0x42,0x42,0x42,0x3C,0x00,0x00},/*"8",24*/
{0x00,0x00,0x00,0x18,0x24,0x42,0x42,0x42,0x64,0x58,0x40,0x40,0x24,0x1C,0x00,0x00},/*"9",25*/
{0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00,0x00,0x18,0x18,0x00,0x00},/*":",26*/
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x08,0x08,0x04},/*";",27*/
{0x00,0x00,0x00,0x40,0x20,0x10,0x08,0x04,0x02,0x04,0x08,0x10,0x20,0x40,0x00,0x00},/*"<",28*/
{0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0x00,0x00,0x00,0x7F,0x00,0x00,0x00,0x00,0x00},/*"=",29*/
{0x00,0x00,0x00,0x02,0x04,0x08,0x10,0x20,0x40,0x20,0x10,0x08,0x04,0x02,0x00,0x00},/*">",30*/
{0x00,0x00,0x00,0x3C,0x42,0x42,0x46,0x40,0x20,0x10,0x10,0x00,0x18,0x18,0x00,0x00},/*"?",31*/
{0x00,0x00,0x00,0x1C,0x22,0x5A,0x55,0x55,0x55,0x55,0x2D,0x42,0x22,0x1C,0x00,0x00},/*"@",32*/
{0x00,0x00,0x00,0x08,0x08,0x18,0x14,0x14,0x24,0x3C,0x22,0x42,0x42,0xE7,0x00,0x00},/*"A",33*/
{0x00,0x00,0x00,0x1F,0x22,0x22,0x22,0x1E,0x22,0x42,0x42,0x42,0x22,0x1F,0x00,0x00},/*"B",34*/
{0x00,0x00,0x00,0x7C,0x42,0x42,0x01,0x01,0x01,0x01,0x01,0x42,0x22,0x1C,0x00,0x00},/*"C",35*/
{0x00,0x00,0x00,0x1F,0x22,0x42,0x42,0x42,0x42,0x42,0x42,0x42,0x22,0x1F,0x00,0x00},/*"D",36*/
{0x00,0x00,0x00,0x3F,0x42,0x12,0x12,0x1E,0x12,0x12,0x02,0x42,0x42,0x3F,0x00,0x00},/*"E",37*/
{0x00,0x00,0x00,0x3F,0x42,0x12,0x12,0x1E,0x12,0x12,0x02,0x02,0x02,0x07,0x00,0x00},/*"F",38*/
{0x00,0x00,0x00,0x3C,0x22,0x22,0x01,0x01,0x01,0x71,0x21,0x22,0x22,0x1C,0x00,0x00},/*"G",39*/
{0x00,0x00,0x00,0xE7,0x42,0x42,0x42,0x42,0x7E,0x42,0x42,0x42,0x42,0xE7,0x00,0x00},/*"H",40*/
{0x00,0x00,0x00,0x3E,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x3E,0x00,0x00},/*"I",41*/
{0x00,0x00,0x00,0x7C,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x11,0x0F},/*"J",42*/
{0x00,0x00,0x00,0x77,0x22,0x12,0x0A,0x0E,0x0A,0x12,0x12,0x22,0x22,0x77,0x00,0x00},/*"K",43*/
{0x00,0x00,0x00,0x07,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x42,0x7F,0x00,0x00},/*"L",44*/
{0x00,0x00,0x00,0x77,0x36,0x36,0x36,0x36,0x2A,0x2A,0x2A,0x2A,0x2A,0x6B,0x00,0x00},/*"M",45*/
{0x00,0x00,0x00,0xE3,0x46,0x46,0x4A,0x4A,0x52,0x52,0x52,0x62,0x62,0x47,0x00,0x00},/*"N",46*/
{0x00,0x00,0x00,0x1C,0x22,0x41,0x41,0x41,0x41,0x41,0x41,0x41,0x22,0x1C,0x00,0x00},/*"O",47*/
{0x00,0x00,0x00,0x3F,0x42,0x42,0x42,0x42,0x3E,0x02,0x02,0x02,0x02,0x07,0x00,0x00},/*"P",48*/
{0x00,0x00,0x00,0x1C,0x22,0x41,0x41,0x41,0x41,0x41,0x4D,0x53,0x32,0x1C,0x60,0x00},/*"Q",49*/
{0x00,0x00,0x00,0x3F,0x42,0x42,0x42,0x3E,0x12,0x12,0x22,0x22,0x42,0xC7,0x00,0x00},/*"R",50*/
{0x00,0x00,0x00,0x7C,0x42,0x42,0x02,0x04,0x18,0x20,0x40,0x42,0x42,0x3E,0x00,0x00},/*"S",51*/
{0x00,0x00,0x00,0x7F,0x49,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x1C,0x00,0x00},/*"T",52*/
{0x00,0x00,0x00,0xE7,0x42,0x42,0x42,0x42,0x42,0x42,0x42,0x42,0x42,0x3C,0x00,0x00},/*"U",53*/
{0x00,0x00,0x00,0xE7,0x42,0x42,0x22,0x24,0x24,0x14,0x14,0x18,0x08,0x08,0x00,0x00},/*"V",54*/
{0x00,0x00,0x00,0x6B,0x49,0x49,0x49,0x49,0x55,0x55,0x36,0x22,0x22,0x22,0x00,0x00},/*"W",55*/
{0x00,0x00,0x00,0xE7,0x42,0x24,0x24,0x18,0x18,0x18,0x24,0x24,0x42,0xE7,0x00,0x00},/*"X",56*/
{0x00,0x00,0x00,0x77,0x22,0x22,0x14,0x14,0x08,0x08,0x08,0x08,0x08,0x1C,0x00,0x00},/*"Y",57*/
{0x00,0x00,0x00,0x7E,0x21,0x20,0x10,0x10,0x08,0x04,0x04,0x42,0x42,0x3F,0x00,0x00},/*"Z",58*/
{0x00,0x78,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x78,0x00},/*"[",59*/
{0x00,0x00,0x02,0x02,0x04,0x04,0x08,0x08,0x08,0x10,0x10,0x20,0x20,0x20,0x40,0x40},/*"\",60*/
{0x00,0x1E,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x1E,0x00},/*"]",61*/
{0x00,0x38,0x44,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"^",62*/
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF},/*"_",63*/
{0x00,0x06,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"`",64*/
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3C,0x42,0x78,0x44,0x42,0x42,0xFC,0x00,0x00},/*"a",65*/
{0x00,0x00,0x00,0x03,0x02,0x02,0x02,0x1A,0x26,0x42,0x42,0x42,0x26,0x1A,0x00,0x00},/*"b",66*/
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x38,0x44,0x02,0x02,0x02,0x44,0x38,0x00,0x00},/*"c",67*/
{0x00,0x00,0x00,0x60,0x40,0x40,0x40,0x78,0x44,0x42,0x42,0x42,0x64,0xD8,0x00,0x00},/*"d",68*/
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3C,0x42,0x7E,0x02,0x02,0x42,0x3C,0x00,0x00},/*"e",69*/
{0x00,0x00,0x00,0xF0,0x88,0x08,0x08,0x7E,0x08,0x08,0x08,0x08,0x08,0x3E,0x00,0x00},/*"f",70*/
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7C,0x22,0x22,0x1C,0x02,0x3C,0x42,0x42,0x3C},/*"g",71*/
{0x00,0x00,0x00,0x03,0x02,0x02,0x02,0x3A,0x46,0x42,0x42,0x42,0x42,0xE7,0x00,0x00},/*"h",72*/
{0x00,0x00,0x00,0x0C,0x0C,0x00,0x00,0x0E,0x08,0x08,0x08,0x08,0x08,0x3E,0x00,0x00},/*"i",73*/
{0x00,0x00,0x00,0x30,0x30,0x00,0x00,0x38,0x20,0x20,0x20,0x20,0x20,0x20,0x22,0x1E},/*"j",74*/
{0x00,0x00,0x00,0x03,0x02,0x02,0x02,0x72,0x12,0x0A,0x16,0x12,0x22,0x77,0x00,0x00},/*"k",75*/
{0x00,0x00,0x00,0x0E,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x3E,0x00,0x00},/*"l",76*/
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0x92,0x92,0x92,0x92,0x92,0xB7,0x00,0x00},/*"m",77*/
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3B,0x46,0x42,0x42,0x42,0x42,0xE7,0x00,0x00},/*"n",78*/
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3C,0x42,0x42,0x42,0x42,0x42,0x3C,0x00,0x00},/*"o",79*/
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1B,0x26,0x42,0x42,0x42,0x22,0x1E,0x02,0x07},/*"p",80*/
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x78,0x44,0x42,0x42,0x42,0x44,0x78,0x40,0xE0},/*"q",81*/
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x77,0x4C,0x04,0x04,0x04,0x04,0x1F,0x00,0x00},/*"r",82*/
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7C,0x42,0x02,0x3C,0x40,0x42,0x3E,0x00,0x00},/*"s",83*/
{0x00,0x00,0x00,0x00,0x00,0x08,0x08,0x3E,0x08,0x08,0x08,0x08,0x08,0x30,0x00,0x00},/*"t",84*/
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x63,0x42,0x42,0x42,0x42,0x62,0xDC,0x00,0x00},/*"u",85*/
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE7,0x42,0x24,0x24,0x14,0x08,0x08,0x00,0x00},/*"v",86*/
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xEB,0x49,0x49,0x55,0x55,0x22,0x22,0x00,0x00},/*"w",87*/
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x76,0x24,0x18,0x18,0x18,0x24,0x6E,0x00,0x00},/*"x",88*/
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE7,0x42,0x24,0x24,0x14,0x18,0x08,0x08,0x07},/*"y",89*/
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7E,0x22,0x10,0x08,0x08,0x44,0x7E,0x00,0x00},/*"z",90*/
{0x00,0xC0,0x20,0x20,0x20,0x20,0x20,0x10,0x20,0x20,0x20,0x20,0x20,0x20,0xC0,0x00},/*"{",91*/
{0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10},/*"|",92*/
{0x00,0x06,0x08,0x08,0x08,0x08,0x08,0x10,0x08,0x08,0x08,0x08,0x08,0x08,0x06,0x00},/*"}",93*/
{0x0C,0x32,0xC2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"~",94*/
};
#endiflcd.c
#include "ascii.h"
typedef unsigned int u32;
typedef unsigned short u16;
#define GPF0CON 0xE0200120
#define GPF1CON 0xE0200140
#define GPF2CON 0xE0200160
#define GPF3CON 0xE0200180
#define GPD0CON 0xE02000A0
#define GPD0DAT 0xE02000A4
#define rGPF0CON (*(volatile unsigned int *)GPF0CON)
#define rGPF1CON (*(volatile unsigned int *)GPF1CON)
#define rGPF2CON (*(volatile unsigned int *)GPF2CON)
#define rGPF3CON (*(volatile unsigned int *)GPF3CON)
#define rGPD0CON (*(volatile unsigned int *)GPD0CON)
#define rGPD0DAT (*(volatile unsigned int *)GPD0DAT)
#define DISPLAY_CONTROL 0xe0107008
#define VIDCON0 0xF8000000
#define VIDCON1 0xF8000004
#define VIDTCON0 0xF8000010
#define VIDTCON1 0xF8000014
#define VIDTCON2 0xF8000018
#define WINCON0 0xF8000020
#define SHADOWCON 0xF8000034
#define VIDOSD0A 0xF8000040
#define VIDOSD0B 0xF8000044
#define VIDOSD0C 0xF8000048
#define VIDW00ADD0B0 0xF80000A0
#define VIDW00ADD1B0 0xF80000D0
#define rDISPLAY_CONTROL (*(volatile unsigned int *)DISPLAY_CONTROL)
#define rVIDCON0 (*(volatile unsigned int *)VIDCON0)
#define rVIDCON1 (*(volatile unsigned int *)VIDCON1)
#define rVIDTCON0 (*(volatile unsigned int *)VIDTCON0)
#define rVIDTCON1 (*(volatile unsigned int *)VIDTCON1)
#define rVIDTCON2 (*(volatile unsigned int *)VIDTCON2)
#define rWINCON0 (*(volatile unsigned int *)WINCON0)
#define rSHADOWCON (*(volatile unsigned int *)SHADOWCON)
#define rVIDOSD0A (*(volatile unsigned int *)VIDOSD0A)
#define rVIDOSD0B (*(volatile unsigned int *)VIDOSD0B)
#define rVIDOSD0C (*(volatile unsigned int *)VIDOSD0C)
#define rVIDW00ADD0B0 (*(volatile unsigned int *)VIDW00ADD0B0)
#define rVIDW00ADD1B0 (*(volatile unsigned int *)VIDW00ADD1B0)
#define HSPW (40)
#define HBPD (10 - 1)
#define HFPD (240 - 1)
#define VSPW (20)
#define VBPD (10 - 1)
#define VFPD (30 - 1)
//FB地址
#define FB_ADDR (0x23000000)
#define ROW (600)
#define COL (1024)
#define HOZVAL (COL-1)
#define LINEVAL (ROW-1)
#define XSIZE COL
#define YSIZE ROW
#define LeftTopX 0
#define LeftTopY 0
#define RightBotX (1024 - 1)
#define RightBotY (600 - 1)
u32 *pfb = (u32 *)FB_ADDR;
void lcd_init()
{
//set gpio as lcd
rGPF0CON = 0x22222222;
rGPF1CON = 0x22222222;
rGPF2CON = 0x22222222;
rGPF3CON = 0x22222222;
//set gpio as PWMTOUT0, open background light
rGPD0CON &= ~(0xf);
rGPD0CON |= (1);
rGPD0DAT &= ~(1);
//set lcd crontol(FIMD) connect outer port(180,rgb,yuv)
rDISPLAY_CONTROL = 2;
//rDISPLAY_CONTROL = 3;
//set RGB interface,RGB parallel format,HCLK_DSYS(166MHz)
rVIDCON0 &= ~((3<<26)|(1<<18)|(1<<2));
//enable lcd
rVIDCON0 |= ((1)|(1<<1));
//set div(VCLK = 166Mhz/(4+1) = 33Mhz) and select div
rVIDCON0 |= ((4<<6) | (1<<4));
//set IVSYNC and IHSYNC high level(Inverted)
rVIDCON1 |= ((1<<5) | (1<<6));
//set Time sequence
rVIDTCON0 = VBPD<<16 | VFPD<<8 | VSPW<<0;
rVIDTCON1 = HBPD<<16 | HFPD<<8 | HSPW<<0;
//set lcd width and length
rVIDTCON2 = ((LINEVAL << 11) | (HOZVAL << 0));
//enable window0 and set 24bpp(RGB888)
rWINCON0 |= 1;
rWINCON0 &= ~(0xf << 2);
rWINCON0 |= (0xB<<2) | (1<<15);
//set lcd coordinate and range
rVIDOSD0A = ((LeftTopX<<11) | (LeftTopY << 0));
rVIDOSD0B = ((RightBotX<<11) | (RightBotY << 0));
rVIDOSD0C = ((LINEVAL + 1) * (HOZVAL + 1));
//set Video frame start and end address(buffer)
rVIDW00ADD0B0 = FB_ADDR;
rVIDW00ADD1B0 = (((HOZVAL + 1)*4 + 0) * (LINEVAL + 1)) & (0xffffff);
//enable channel 0 to transmit data
rSHADOWCON = 0x1;
}
//set pic color
static void lcd_draw_pic_color(u32 x,u32 y,u32 color)
{
*(pfb + COL * y + x) = color;
}
//init lcd background
void init_background(unsigned int color)
{
u32 i, j;
for (j=0; j=0)
{
if(dy >= 0) // dy>=0
{
if(dx>=dy) // 1/8 octant
{
e=dy-dx/2;
while(x1<=x2)
{
lcd_draw_pic_color(x1,y1,color);
if(e>0){y1+=1;e-=dx;}
x1+=1;
e+=dy;
}
}
else // 2/8 octant
{
e=dx-dy/2;
while(y1<=y2)
{
lcd_draw_pic_color(x1,y1,color);
if(e>0){x1+=1;e-=dy;}
y1+=1;
e+=dx;
}
}
}
else // dy<0
{
dy=-dy; // dy=abs(dy)
if(dx>=dy) // 8/8 octant
{
e=dy-dx/2;
while(x1<=x2)
{
lcd_draw_pic_color(x1,y1,color);
if(e>0){y1-=1;e-=dx;}
x1+=1;
e+=dy;
}
}
else // 7/8 octant
{
e=dx-dy/2;
while(y1>=y2)
{
lcd_draw_pic_color(x1,y1,color);
if(e>0){x1+=1;e-=dy;}
y1-=1;
e+=dx;
}
}
}
}
else //dx<0
{
dx=-dx; //dx=abs(dx)
if(dy >= 0) // dy>=0
{
if(dx>=dy) // 4/8 octant
{
e=dy-dx/2;
while(x1>=x2)
{
lcd_draw_pic_color(x1,y1,color);
if(e>0){y1+=1;e-=dx;}
x1-=1;
e+=dy;
}
}
else // 3/8 octant
{
e=dx-dy/2;
while(y1<=y2)
{
lcd_draw_pic_color(x1,y1,color);
if(e>0){x1-=1;e-=dy;}
y1+=1;
e+=dx;
}
}
}
else // dy<0
{
dy=-dy; // dy=abs(dy)
if(dx>=dy) // 5/8 octant
{
e=dy-dx/2;
while(x1>=x2)
{
lcd_draw_pic_color(x1,y1,color);
if(e>0){y1-=1;e-=dx;}
x1-=1;
e+=dy;
}
}
else // 6/8 octant
{
e=dx-dy/2;
while(y1>=y2)
{
lcd_draw_pic_color(x1,y1,color);
if(e>0){x1-=1;e-=dy;}
y1-=1;
e+=dx;
}
}
}
}
}
//draw circle , Center of a circle (centerX, centerY),radius,color
void lcd_draw_circle(unsigned int centerX, unsigned int centerY, unsigned int radius, unsigned int color)
{
int x,y ;
int tempX,tempY;;
int SquareOfR = radius*radius;
for(y=0; y=centerX)
{
tempY=centerY-y;
tempX=x-centerX;
}
else if(y>=centerY&& x<=centerX)
{
tempY=y-centerY;
tempX=centerX-x;
}
else
{
tempY = y-centerY;
tempX = x-centerX;
}
if ((tempY*tempY+tempX*tempX)<=SquareOfR)
lcd_draw_pic_color(x, y, color);
}
}
}
//draw letter,posion (x, y),color,data(Font information)
static void show_8_16(unsigned int x, unsigned int y, unsigned int color, unsigned char *data)
{
//count:recodes pix that using
int i, j, count = 0;
for (j=y; j<(y+16); j++)
{
for (i=x; i<(x+8); i++)
{
if (i= XSIZE)
{
x -= XSIZE; //\r
y += 16; //\n
}
}
}
//appear the picture of 800×480,and the picture of font information in pData
void lcd_appear_picture(const unsigned char *pData)
{
u32 x, y, color, p = 0;
for (y=0; y<600; y++)
{
for (x=0; x<1024; x++)
{
color = ((pData[p+2] << 0) | (pData[p+1] << 8) | (pData[p+0] << 16));
lcd_draw_pic_color(x, y, color);
p += 3;
}
}
} env.h
void env_init();
void print_env();
void set_env(char *name,char *val);
void delete_env(char *name);env.c
#include "string.h"
#include "stdio.h"
#define PARAM_NUM 10
#define PARAM_NAME 14
#define PARAM_VAL 128
char global_param_name[PARAM_NUM][PARAM_NAME] = {'\0'};
char global_param_val[PARAM_NUM][PARAM_VAL] = {'\0'};
void env_init()
{
strcpy(global_param_name[0],"bootdealy");
strcpy(global_param_val[0],"3");
}
void print_env()
{
unsigned int num;
for(num = 0;num < PARAM_NUM;num++)
{
if(strlen(global_param_name[num]) > 0)
printf("%s=%s\r\n",global_param_name[num],global_param_val[num]);
}
}
void set_env(char *name , char *val)
{
unsigned int num;
for(num = 0;num < PARAM_NUM;num++)
{
if(!(strcmp(global_param_name[num],name)))
{
memset(global_param_val[num],'\0',PARAM_VAL);
strcpy(global_param_val[num],val);
return ;
}
}
for(num = 0;num < PARAM_NUM;num++)
{
if(strlen(global_param_name[num]) == 0)
{
strcpy(global_param_name[num],name);
memset(global_param_val[num],'\0',PARAM_VAL);
strcpy(global_param_val[num],val);
return ;
}
}
printf("env is full\n");
}
void delete_env(char *name)
{
unsigned int num;
if(!(strcmp(name,"bootdealy")))
{
printf("system param can not delete\r\n");
return ;
}
for(num = 0;num < PARAM_NUM;num++)
{
if(!(strcmp(global_param_name[num],name)))
{
memset(global_param_val[num],'\0',PARAM_VAL);
memset(global_param_name[num],'\0',PARAM_NAME);
return ;
}
}
printf("have no env\r\n");
}link.lds
SECTIONS
{
. = 0x23e00000;
.text :
{
start.o
* (.text)
}
.data :
{
* (.data)
}
bss_start = .;
.bss :
{
* (.bss)
}
bss_end = .;
}Makefile
CC = arm-linux-gcc
LD = arm-linux-ld
OBJCOPY = arm-linux-objcopy
OBJDUMP = arm-linux-objdump
INCDIR := $(shell pwd)
#预处理器的flag，flag就是编译器可选的选项
CPPFLAGS := -nostdlib -nostdinc -I$(INCDIR)/include
#C编译器的flag
CFLAGS := -Wall -O2 -fno-builtin
export CC LD OBJCOPY OBJDUMP CPPFLAGS CFLAGS
objs := start.o uart_printf.o main.o led.o io.o cmd.o lcd.o adc.o buzzer.o env.o interrupt.o
objs += lib/libc.a
led.bin:$(objs)
$(LD) -Tlink.lds -o sd2.elf $^
$(OBJCOPY) -O binary sd2.elf sd2.bin
$(OBJDUMP) -D sd2.elf > sd2.dis
lib/libc.a:
cd lib; make; cd ..
%.o:%.S
$(CC) $(CPPFLAGS) $(CFLAGS) -o $@ $< -c
%.o:%.c
$(CC) $(CPPFLAGS) $(CFLAGS) -o $@ $< -c
clean:
rm *.o *.elf *.bin *.dis mkv210 -f
cd lib; make clean; cd ..