刘夏真的简历中国科学院计算机所,专家人才库数据----中国科学院计算技术研究所...

[1] L. Chao, X. Peng, Z. Xu, L. Zhang, “Ecosystem of Things: Hardware, Software, and Architecture”, Proceedings of the IEEE, 107(8), 2019. (CCF A)

[2] Y. Wang, Y. Han, L. Zhang, H. Li, X. Li, "ProPRAM: Exploiting the Transparent Logic Resources in Non-Volatile Memory for Near Data Computing", ACM/IEEE 52nd Design Automation Conference (DAC), 47-52, July, 2015. (CCF A)

[3] JB. Dong, L. Zhang, YH. Han, Y. Wang, XW. Li, "Wear Rate Leveling: Lifetime Enhancement of PRAM with Endurance Variation", ACM/IEEE 48th Design Automation Conference (DAC), 972-977, Aug. 2011. (CCF A)

[4] Y. Wang, Y. Han, H. Li, L. Zhang, Y. Cheng, X. Li, "PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM", IEEE Trans. on Very Large Scale Integration (TVLSI) Systems, 24 (5), pp. 1613-1625, 2016.

[5] Y. Wang, L. Zhang, Y. Han, H. Li, X. Li, "Data Remapping for Static NUCA in Degradable Chip Multiprocessors", IEEE Trans. on Very Large Scale Integration (TVLSI) Systems, 23(5), pp. 879-892, May, 2015.

[6] Y. Wang, YH. Han, L. Zhang, BZ. Fu, C. Liu, HW. Li, XW. Li, "Economizing TSV Resources in 3-D Network-on-Chip Design", IEEE Trans. on Very Large Scale Integration (TVLSI) Systems, 23(3), 493-506, March, 2015.

[7] Y. Wang, L. Zhang, YH. Han, HW. Li, "Reinventing Memory System Design for Many-Accelerator Architecture", Journal of Computer Science and Technology (JCST), 29 (2), 273-280, Mar. 2014.

[8] P. Chen, L. Zhang, YH. Han, YJ. Chen, "A General-Purpose Many-Accelerator Architecture Based on Dataflow Graph Clustering of Applications", Journal of Computer Science and Technology (JCST), 29 (2), 239-246, , Mar. 2014.

[9] YQ. Cheng, L. Zhang, YH. Han, XW. Li, "Thermal-Constrained Task Allocation for Interconnect Energy Reduction in 3-D Homogeneous MPSoCs", IEEE Trans. on Very Large Scale Integration (TVLSI) Systems, 21(2), 239-249, Feb. 2013.

[10] YQ. Cheng, L. Zhang, YH. Han, XW. Li, "TSV Minimization for Circuit-Partitioned 3D SoC Test Wrapper Design", Journal of Computer Science and Technology (JCST), 28 (1): 119-128, Jan. 2013.

[11] ZW. Xu, XH. Peng, L. Zhang, D. Li, NH. Sun, "The Φ-Stack for Smart Web of Things", ACM/IEEE Symposium on Edge Computing(SEC), 2017.

[12] Y. Wang, L. Zhang, YH. Han, HW. Li, XW. Li, "Flex Memory: Exploiting and Managing Abundant Off-chip Optical Bandwidth", ACM/IEEE Design, Automation and Test in Europe (DATE), 1-6, May 2011. (CCF B)

[13] C. Liu, L. Zhang, YH. Han, XW. Li, "A Resilient On-Chip Router Design Through Data Path Salvaging", ACM/IEEE 16th Asia South Pacific Design Automation Conference (ASP-DAC), March 2011.

[14] C. Liu, L. Zhang, YH. Han, XW. Li, "Vertical Interconnects Squeezing in Symmetric 3D Mesh Network-on-Chip", ACM/IEEE 16th Asia South Pacific Design Automation Conference (ASP-DAC), March 2011.

[15] WW. Chen, Y. Wang, S. Yang, L. Zhang, C. Liu, "You Only Search Once: A Fast Automation Framework for Single-Stage DNN/Accelerator Co-design", IEEE/ACM Proceedings of Design, Automation and Test in Europe (DATE), 2020.

[16] L. Zhang, Yinhe Han, Qiang Xu, Xiaowei Li and Huawei Li. "On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 17(9), pp.1173-1186, Sep. 2009.

[17] L. Zhang, Y. Yu, J. Dong, Y. Han, S. Ren, X. Li. "Performance-Asymmetry-Aware Topology Virtualization for Defect-Tolerant NoC-based Many-core Processors", IEEE/ACM Design, Automation and Test in Europe (DATE), pp. 1566-1571, Dresden, Germany, March 8-12, 2010.

[18] L. Zhang, Y. Han, Q. Xu and X. Li. "Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology", IEEE/ACM Design, Automation and Test in Europe (DATE), pp: 891-896, Munich Germany, March 10-14, 2008.