(原创)多功能数字钟(Digital Logic)(DE2)(QuartusII)

Abstract

将电路分成不同的层次和模块分别进行设计,然后组合,实现电路功能。

 

Instruction

数字钟的功能:

  1. 准确计时,以数字显示时、分、秒;
  2. 具有分、时校时功能;
  3. 整点报时;
  4. 闹钟;

 

指定:

/////////////////////////////////////////////////////////////////////
   管脚               //     端口
-----------------------------------------------------------
   SW0                       复位(0有效)
-----------------------------------------------------------
   SW1                       校时调分钟
----------------------------------------------------------
   SW2                       校时调小时
----------------------------------------------------------
   SW3                       mode(闹钟定时模式)
----------------------------------------------------------
   SW4                       设置闹钟的分钟
----------------------------------------------------------
   SW5                       设置闹钟的小时
----------------------------------------------------------
   SW6                       ctrl_bell(关闭闹钟0有效)
----------------------------------------------------------
   SW7                       输出时钟选择(0-1hz,1-5hz)
----------------------------------------------------------
   CLOCK_50                  输入时钟
----------------------------------------------------------
   HEX5--4                   显示小时
----------------------------------------------------------
   HEX3--2                   显示分钟
----------------------------------------------------------
   HEX1--0                   显示秒
----------------------------------------------------------
   LEDG8                     表示闹钟或整点报时
////////////////////////////////////////////////////////////////////

 

分析:

数字钟组成框图

 

数字钟主体电路的设计

1. 模24计数器

//counter24.v

  
    
1 // filename :counter24.v (BCD : 0--23)
2 module counter24(CntH,CntL,ncR,EN,CP);
3 input CP,ncR,EN;
4 output [ 3 : 0 ]CntH,CntL;
5 reg [ 3 : 0 ]CntH,CntL;
6
7 always @( posedge CP, negedge ncR)
8 begin
9 if ( ~ ncR)
10 {CntH,CntL} <= 8 ' h00;
11 else if ( ~ EN)
12 {CntH,CntL} <= {CntH,CntL};
13 else if ((CntH > 2 ) || (CntL > 9 ) || ((CntH == 2 ) && (CntL >= 3 )))
14 {CntH,CntL} <= 8 ' h00;
15 else if ((CntH == 2 ) && (CntL < 3 ))
16 begin
17 CntH <= CntH;
18 CntL <= CntL + 1 ' b1;
19 end
20 else if (CntL == 9 )
21 begin
22 CntH <= CntH + 1 ' b1;
23 CntL <= 4 ' b0000;
24 end
25 else
26 begin
27 CntH <= CntH;
28 CntL <= CntL + 1 ' b1;
29 end
30 end
31
32 endmodule

 

2. 模60计数器

60进制计数器的层次结构

//counter60.v

 

  
    
1 // countuer 60
2
3 // counter10.v (BCD: 0--9)
4 module counter10(Q,ncR,EN,CP);
5 input CP,ncR,EN;
6 output reg [ 3 : 0 ]Q;
7
8 always @( posedge CP, negedge ncR)
9 begin
10 if ( ~ ncR)
11 Q <= 4 ' b0000;
12 else if ( ~ EN)
13 Q <= Q;
14 else if (Q == 4 ' b1001)
15 Q <= 4 ' b0000;
16 else
17 Q <= Q + 1 ' b1;
18 end
19 endmodule
20
21 // counter6.v(BCD: 0--5)
22 module counter6(Q,ncR,EN,CP);
23 input CP,ncR,EN;
24 output reg [ 3 : 0 ]Q;
25
26 always @( posedge CP, negedge ncR)
27 begin
28 if ( ~ ncR)
29 Q <= 4 ' b0000;
30 else if ( ~ EN)
31 Q <= Q;
32 else if (Q == 4 ' b0101)
33 Q <= 4 ' b0000;
34 else
35 Q <= Q + 1 ' b1;
36 end
37 endmodule
38
39 // counter60.v(BCD:0--59)
40 module counter60(Cnt,ncR,EN,CP);
41 input CP,ncR,EN;
42 output [ 7 : 0 ]Cnt;
43 wire [ 7 : 0 ]Cnt;
44 wire ENP;
45
46 counter10 UC0(Cnt[ 3 : 0 ],ncR,EN,CP);
47 counter6 UC1(Cnt[ 7 : 4 ],ncR,ENP,CP);
48
49 assign ENP = (Cnt[ 3 : 0 ] == 4 ' h9);
50 endmodule

3. 主体电路

//top_clock.v

 
   
     
1 // top_clock.v
2 module top_clock(Hour,Minute,Second,_1HZ,ncR,AdjMinKey,AdjHrKey);
3 input _1HZ,ncR,AdjMinKey,AdjHrKey;
4 output wire [ 7 : 0 ]Hour,Minute,Second;
5 supply1 Vdd;
6 wire MinCP,HrCP;
7
8 // Hour:Minute:Second counter
9 counter60 UT1(Second,ncR,Vdd,_1HZ); // second counter
10 counter60 UT2(Minute,ncR,Vdd, ~ MinCP); // minute counter
11 counter24 UT3(Hour[ 7 : 4 ],Hour[ 3 : 0 ],ncR,Vdd, ~ HrCP); // hour counter
12
13 // generate singal of minute counter
14 assign MinCP = AdjMinKey ? _1HZ:(Second == 8 ' h59);
15 // generate singal of hour counter
16 assign HrCP = AdjHrKey ? _1HZ:({Minute,Second} == 16 ' h5959);
17
18 endmodule
 

方框图:

top_clock方框

仿真结果

top_clock_01

top_clock_02

4. 分频模块

//参考无双的万用分频器

 

扩展电路的设计

1. 整点报时

//radio.v

  
    
1 // Radio.v
2 module Radio(alarm_radio,minute,second,_1khz,_500hz);
3 input _1khz,_500hz;
4 input [ 7 : 0 ]minute,second;
5 output reg alarm_radio;
6
7 always @(minute or second)
8 if (minute == 8 ' h59)
9 case (second)
10 8 ' h51,
11 8 ' h53,
12 8 ' h55,
13 8 ' h57:alarm_radio=_500hz;
14 8 ' h59:alarm_radio=_1khz;
15 default :alarm_radio = 1 ' b0;
16 endcase
17 else alarm_radio = 1 ' b0;
18
19 endmodule

2.闹钟

//bell.v

 

  
    
1 // Bell.v
2 module Bell(alarm_clock,set_hr,set_min,hour,minute,
3 second,sethrkey,setminkey,_1khz,_500hz,
4 _1hz,ctrlbell);
5 output alarm_clock;
6 output [ 7 : 0 ]set_hr,set_min;
7 wire alarm_clock;
8 input _1khz,_500hz,_1hz;
9 input sethrkey,setminkey;
10 input ctrlbell;
11 input [ 7 : 0 ]hour,minute,second;
12
13 supply1 Vdd;
14 wire hrh_equ,hrl_equ,minh_equ,minl_equ;
15 wire time_equ;
16
17 counter60 SU1(set_min,Vdd,setminkey,_1hz);
18 counter24 SU2(set_hr[ 7 : 4 ],set_hr[ 3 : 0 ],Vdd,sethrkey,_1hz);
19
20 // comparate the set time
21 _4bitcomparator SU4(hrh_equ,set_hr[ 7 : 4 ],hour[ 7 : 4 ]);
22 _4bitcomparator SU5(hrl_equ,set_hr[ 3 : 0 ],hour[ 3 : 0 ]);
23 _4bitcomparator SU6(minh_equ,set_min[ 7 : 4 ],minute[ 7 : 4 ]);
24 _4bitcomparator SU7(minl_equ,set_min[ 3 : 0 ],minute[ 3 : 0 ]);
25
26 assign time_equ = (hrh_equ && hrl_equ && minh_equ && minl_equ);
27 assign alarm_clock = ctrlbell ? (time_equ && (((second[ 0 ] == 1 ' b1)&&_500hz)
28 || ((second[ 0 ] == 1 ' b0)&&_1khz))):1 ' b0;
29 endmodule
30
31 // 4bitcomparator.v
32 module _4bitcomparator(equ,a,b);
33 input [ 3 : 0 ]a,b;
34 output equ;
35
36 assign equ = (a == b);
37 endmodule

多功能数字钟顶层电路设计

//complete_clock.v

另一种实现方式:方框图

complete_clock

Conclusion

数字钟也算是一个经典的课设,尝试在DE2上实现。当然功能还可扩展,唯一待解决的问题是DE2没有配置蜂鸣器,暂时用LEDG8接收500hz和1Khz的频率来代替蜂鸣器的效果。(不够完美:()。

Reference

罗杰 <Verilog HDL与数字ASIC设计基础> 华科

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