【HDLBits刷题】Exams/2014 q4a.

Consider the n-bit shift register circuit shown below:

Write a Verilog module named top_module for one stage of this circuit, including both the flip-flop and multiplexers.

1、第一种方法是通过抽象方法，从电路最后面看，写出Q输出：

module top_module (
    input clk,
    input w, R, E, L,
    output Q
);

    wire temp1, temp2;

    assign temp1 = E ? w:Q; 
    assign temp2 = L ? R:temp1;
    //与上题类似，不做赘述

    always @ (posedge clk)
        begin
           Q <= temp2; 
        end

endmodule


// 下面一样的
****************************************

module top_module (
    input clk,
    input w, R, E, L,
    output Q
);
    always @(posedge clk)begin
        if(E==0&&L==0)
            Q <=Q;
        else if(L==1)
            Q <= R;
        else
            Q <= w;
    end
endmodule

 2、第二种是写单个模块，然后用结构型建模把子模块都连接起来

略