Follow tb_code_starders

The stardes define the coding of Verilog,SV and UVM to fullfill Testbench.

1 File Orgnization

1.1 File struc

Rule 1: UVM component should all be packaged.
Packages:
0.__agt_pkg;
1.__env_pkg;
2.__sequences_pkg;
3.__tests_pkg;
Rule 2: Import package inside tb_top;
Rule 3: The file directery in TestBench:
–dv //top root-direc
---------script/
---------tool/
---------common/
---------common_vip/ VIP/UVC
---------ss_xxxx //SoC and subsystem and module direct
-----------------scripts
-----------------filelist //TB UVC VIP
-----------------sim
-----------------dut
-----------------tb
-----------------cfg
-----------------cov
-----------------sva
-----------------interface
-----------------src
----------------------env
----------------------regs
----------------------agents
----------------------sequences
----------------------virtual_sequences //virtual_sequences,virtual_sequencers
-----------------test

1.2 File format

Note must use // ,NO /* */

package pss_env_pkg;
        //Starderd UVM import & include
        import uvm_pkg::*;
        `include "uvm_macros.svh"
        
        //Any further package imports::
        import gpio_env_pkg::*;
        import spi_env_pkg::*;
        import ahb_env_pkg::*;
        import spi_agent_pkg::*;
        import gpio_agent_pkg::*;
        import pss_reg_pkg::8;
        import intr_pkg::*;

        //includes:
        `include "pss_env_config.svh"
        `include "pss_env.svh"
        
endpackage: pss_env_pkg

1.3 file suffix

1. file’s suffix
   file suffix
   Verilog . v
   Verilog include .vh
   SystemVerilog .sv
   SystemVerilog inlcude .svh
   Assertion .sva
   C .c
   c include .h

1.4 class interface

Name : use small xx_xx_2 ;
abbresion : Every class/interface must use a word’s abbr.
Consistent: files’name is the same with class or interface.
uvm_component :
TestBecnch: *_tb_top.sv
Package : *_pkg.sv
Sequence : *_seq.sv
Driver : *_drv.sv
Monitor: *_mon.sv
uvm_env: *_env.sv
config : *_cfg.sv
Agent : *_agt.sv
Interrfacee: *_if.sv2Agcr@m?

1.5 Paramter and Const

1.`define paramter must use Big A and use ‘_’;
2.the prefix must use function;

1.6 Varia

varia must be noun or adj + non;

1.7 Enter

1. one line foucs on do one thing.
2. Every Two Function must use enter.
3. Prohibit using noting code to save the code,the code must be deleted.
4. Let the code have anote itself.

1.8 begin…end

begin…end must be with if,else,for,d,while ,even it has one line code.

2 how to abbrev

ref blog: https://blog.csdn.net/heartdreamplus/article/details/86171272

2.1 Ways to abbrev

1.约定法
在实际工作中大家经常使用的缩写方法，比如read缩写为rd,address缩写为addr;
2.辅音法
辅音法使用单词中主要的辅音字母（以发音为准）进行缩写，比如delay缩写为dly,clear缩写为clr;
一些辅音法中对r以及元音（a/e/i/o/u）有着特殊的处理，比如clear中保持r,clock缩写为clk,而省略第二个c,对于以元音开始的单词，一般将第一个元音保留，比如average的缩写为avg;

3.词首法
词首法使用单词的首部，比如address缩写为addr，acknowledge缩写为ack;
4.词组法
针对多个单词的缩写，取每个单词的首字母组合而成，例如Start of Packet即SOP。
5.混合法
混合法采用其他各种缩写方法来形成新的缩写，例如write data 即wdata;