Verilog刷题[hdlbits] ：Adder100i

题目：Adder100i

Create a 100-bit binary ripple-carry adder by instantiating 100 full adders. The adder adds two 100-bit numbers and a carry-in to produce a 100-bit sum and carry out. To encourage you to actually instantiate full adders, also output the carry-out from each full adder in the ripple-carry adder. cout[99] is the final carry-out from the last full adder, and is the carry-out you usually see.

• 通过实例化100个全加法器来创建一个100位二进制纹波进位加法器。加法器将两个100位的数字和一个进位相加，产生一个100位的和并执行。为了鼓励您实际实例化全加法器，还可以输出波纹进位加法器中每个全加法器的执行值。Cout[99]是最后一个全加法器的最后一个执行，也是您通常看到的执行。

Hint…

• 提示……

There are many full adders to instantiate. An instance array or generate statement would help here.

• 有许多完整加法器需要实例化。实例数组或生成语句在这里会有所帮助。

module top_module( 
    input [99:0] a, b,
    input cin,
    output [99:0] cout,
    output [99:0] sum );
    
    reg [6:0] i;
    always@(*) begin
        for(i=7'd0;i<=7'd99;i=i+7'd1)
            if(i==7'd0)
               {cout[i],sum[i]}=  a[i] + b[i] + cin;
            else
               {cout[i],sum[i]}=  a[i] + b[i] + cout[i-7'd1];
    end
endmodule


module top_module( 
    input [99:0] a, b,
    input cin,
    output [99:0] cout,
    output [99:0] sum );
    
    reg [6:0] i;
    always@(*) begin
        for(i=7'd0;i<=7'd99;i=i+7'd1)
            if(i==7'd0)
                begin
                sum[i] =  a[i] ^ b[i] ^ cin;
                cout[i]=  (a[i]&b[i])|((a[i]^b[i])&cin);
                end    
            else
                begin
                sum[i] =  a[i] ^ b[i] ^ cout[i-7'd1];
                cout[i]=  (a[i]&b[i])|((a[i]^b[i])&cout[i-7'd1]);
                end
    end
endmodule