基于Robei EDA--边沿检测电路
一、上来画波形图
上升沿检测
{signal: [
{name: 'clk', wave: 'p.........|............'},
{name: 'rerset', wave: 'lh......|..............'},
{name: 'a', wave: 'l......hl..'},
{name: 'a_dly', wave: 'l.......hl..'},
{name: 'a_dly~', wave: 'h.......lh..'},
{name: 'a_dly~', wave: 'l......hl..'},
],
config: { hscale: 2,
skin: "narrow"
}
}
下降沿检测
{signal: [
{name: 'clk', wave: 'p.........|............'},
{name: 'rerset', wave: 'lh......|..............'},
{name: 'a', wave: 'h......lh..'},
{name: 'a_dly', wave: 'h.......lh..'},
{name: 'a_dly~', wave: 'l.......hl..'},
{name: 'a_dly~', wave: 'l......hl..'},
],
config: { hscale: 2,
skin: "narrow"
}
}
双边沿检测
{signal: [
{name: 'clk', wave: 'p.........|............'},
{name: 'rerset', wave: 'lh......|..............'},
{name: 'a', wave: 'l.....h.l..'},
{name: 'a_dly', wave: 'l......h.l..'},
{name: 'a_dly~', wave: 'h......l.h..'},
{name: 'a_dly~', wave: 'l.....hlhl.'},
],
config: { hscale: 2,
skin: "narrow"
}
}
二、Robei EDA编写代码
edge_check.v
reg a_dly;
always@(posedge clk or negedge reset)
if(reset == 0) begin
a_dly<= 1'b0;
end
else a_dly <= a;
assign rising = a&~a_dly;//取上升沿
assign falling =~a&a_dly;//取下降沿
assign both = a ^ a_dly; //取双边沿edge_check_tb.v
always #10 clk = ~clk;
initial begin
clk = 1;
reset = 0;
a = 0;
#11
reset = 1;
#110
a = 1;
#40
a = 0;
#60
a = 1;
#50;
a = 0;
#10;
$finish;
end
