verilog刷题笔记

verilog language

Adder100i（100位加法器）

module top_module( 
    input [99:0] a, b,
    input cin,
    output [99:0] cout,
    output [99:0] sum );
    always @(*)begin
        sum[0] = a[0] ^ b[0] ^ cin;
        cout[0] = a[0] & b[0] | a[0]&cin | b[0]&cin;
        for(int i = 1; i < 100; i++)begin
            sum[i] = a[i]^ b[i] ^ cout[i - 1];
            cout[i] = a[i]&b[i] | a[i]&cout[i - 1] | b[i]&cout[i - 1];
        end
    end
endmodule

注意

cout[i] = a[i]&b[i] | a[i]&cout[i - 1] | b[i]&cout[i - 1];

不能写成

cout[i] = a[i]&&b[i] + a[i]&&cout[i - 1] + b[i]&&cout[i - 1];

Mt2015 eq2

verilog中if，case语句必须写在always中，case后不需要加begin，最后以endcase结尾

Circuits

Sequential Logic

D Latch

1. Latches are level-sensitive (not edge-sensitive) circuits, so in an always block, they use level-sensitive sensitivity lists.
2. However, they are still sequential elements, so should use non-blocking assignments.
3. A D-latch acts like a wire (or non-inverting buffer) when enabled, and preserves the current value when disabled.

module top_module (
    input d, 
    input ena,
    output q);
    always@(*)begin
        if(ena)
            q = d;
    end
endmodule

如何正确理解latch？
写在always模块里，可以多次赋值，如果assign只能赋值一次？
always语句不能嵌套。

关于初始化
如果assign，之后不能再更改，因为assign=0是直接接地的意思，之后永远为0，因此，需要在always@（*）中去进行初始化