1: library IEEE;
2: Use IEEE.std_logic_1164.all;
3: Use IEEE.numeric_std.all;
4:
5: entity VHSEG7_Controller is
6: generic (SEG7_NUM: integer :=8;
7: DATA_WIDTH: integer:=32;
8: ADDR_WIDTH: integer :=3
9: );
10: port(csi_clockreset_clk: in std_logic;
11: csi_clockreset_reset_n: in std_logic;
12: avs_s1_write: in std_logic;
13: avs_s1_address: in std_logic_vector( ADDR_WIDTH -1 downto 0);
14: avs_s1_writedata: in std_logic_vector(DATA_WIDTH -1 downto 0);
15: avs_s1_export_oHEX: out std_logic_vector(SEG7_NUM * 8 -1 downto 0));
16: end entity VHSEG7_Controller;
17:
18: architecture europa of VHSEG7_Controller is
19: signal write_data: unsigned(DATA_WIDTH -1 downto 0);
20: signal base_index: unsigned(SEG7_NUM -1 downto 0);
21: signal reg_file: unsigned(SEG7_NUM * 8 -1 downto 0);
22: signal Taddress: unsigned(ADDR_WIDTH -1 downto 0);
23:
24: begin
25: avs_s1_export_oHEX <= std_logic_vector(NOT reg_file);
26: seq:process( csi_clockreset_clk)
27: begin
28: if(csi_clockreset_reset_n ='0') then
29: base_index <= to_unsigned(0,SEG7_NUM);
30: write_data <= to_unsigned(0,DATA_WIDTH);
31: for i in 0 to SEG7_NUM * 8 -1 loop
32: reg_file(i) <='1';
33: end loop;
34: else
35: if(avs_s1_write = '1') then
36: write_data<=unsigned(avs_s1_writedata);
37: Taddress <= unsigned(avs_s1_address);
38: --base_index <= Taddress * 8;
39: base_index <= unsigned("00" & avs_s1_address & "000");
40: for i in 0 to 7 loop
41: reg_file(to_integer(base_index+i)) <= write_data(i);
42: end loop;
43: end if;
44: end if;
45: end process seq;
46: end architecture europa;
47:
48:
