带帧同步检测的RS232通信

其中 data_process模块：

  
  

   
   
   
    1 
   
   module
   
    data_process

   
    2 
   
   (

   
    3 
   
    clk,

   
    4 
   
    valid,

   
    5 
   
    rst_n,

   
    6 
   
    data_from_sp,

   
    7 
   
    data_out,

   
    8 
   
    flag,

   
    9 
   
    clr, 

   
   10 
   
    data_out_en

   
   11 
   
   );

   
   12 
   
   

   
   13 
   
    
   
   input
   
    clk;

   
   14 
   
    
   
   input
   
    valid
   
   /*
   
   synthesis keep
   
   */
   
   ;

   
   15 
   
    
   
   input
   
    rst_n;

   
   16 
   
   input
   
    [
   
   9
   
   :
   
   0
   
   ] data_from_sp
   
   /*
   
   synthesis keep
   
   */
   
   ;

   
   17 
   
   

   
   18 
   
   output
   
    [
   
   7
   
   :
   
   0
   
   ] data_out;

   
   19 
   
   output
   
    data_out_en;

   
   20 
   
   output
   
    clr;

   
   21 
   
   output
   
    [
   
   3
   
   :
   
   0
   
   ] flag;

   
   22 
   
   

   
   23 
   
   reg
   
    [
   
   3
   
   :
   
   0
   
   ] flag;

   
   24 
   
   reg
   
    [
   
   7
   
   :
   
   0
   
   ] data_out_r;

   
   25 
   
   reg
   
    data_out_en
   
   /*
   
   synthesis noprune
   
   */
   
   ;

   
   26 
   
   

   
   27 
   
   always
   
    @ (
   
   posedge
   
    clk 
   
   or
   
    
   
   negedge
   
    rst_n)

   
   28 
   
   begin
   
   

   
   29 
   
    
   
   if
   
    (
   
   !
   
   rst_n)

   
   30 
   
    
   
   begin
   
   

   
   31 
   
    data_out_r 
   
   <=
   
    
   
   8
   
   '
   
   b1111_1111;
   
   

   
   32 
   
    data_out_en 
   
   <=
   
    
   
   1
   
   '
   
   b0;
   
   

   
   33 
   
    flag 
   
   <=
   
    
   
   4
   
   '
   
   b0000;
   
   

   
   34 
   
    
   
   end
   
   

   
   35 
   
    
   
   else
   
    
   
   if
   
    (valid)

   
   36 
   
    
   
   begin
   
   

   
   37 
   
    
   
   if
   
   ((data_from_sp[
   
   9
   
   ]
   
   ==
   
   1
   
   '
   
   b1)&&(data_from_sp[0]==1
   
   '
   
   b0)
   
   ||
   
   (flag
   
   !=
   
   4
   
   '
   
   b0000))
   
   

   
   38 
   
    
   
   begin
   
    

   
   39 
   
    
   
   if
   
   (flag
   
   ==
   
   4
   
   '
   
   b0000)
   
   

   
   40 
   
    
   
   begin
   
   

   
   41 
   
    data_out_r[
   
   7
   
   :
   
   0
   
   ] 
   
   <=
   
    data_from_sp[
   
   8
   
   :
   
   1
   
   ];

   
   42 
   
    data_out_en 
   
   <=
   
    
   
   1
   
   '
   
   b1;
   
   

   
   43 
   
    flag 
   
   <=
   
    flag 
   
   +
   
   1
   
   '
   
   b1;
   
   

   
   44 
   
    
   
   end
   
   

   
   45 
   
    
   
   else
   
    
   
   if
   
   (flag
   
   ==
   
   4
   
   '
   
   d9)
   
   

   
   46 
   
    
   
   begin
   
   

   
   47 
   
    flag 
   
   <=
   
    
   
   4
   
   '
   
   b0000;
   
   

   
   48 
   
    data_out_en 
   
   <=
   
    
   
   1
   
   '
   
   b0;
   
   

   
   49 
   
    data_out_r 
   
   <=
   
    
   
   8
   
   '
   
   b1111_1111;
   
   

   
   50 
   
    
   
   end
   
    

   
   51 
   
    
   
   else
   
    

   
   52 
   
    
   
   begin
   
   

   
   53 
   
    flag 
   
   <=
   
    flag 
   
   +
   
   1
   
   '
   
   b1;
   
   

   
   54 
   
    data_out_en 
   
   <=
   
    
   
   1
   
   '
   
   b0;
   
   

   
   55 
   
    data_out_r 
   
   <=
   
    
   
   8
   
   '
   
   b1111_1111;
   
   

   
   56 
   
    
   
   end
   
   

   
   57 
   
    
   
   end
   
   

   
   58 
   
    
   
   else
   
   

   
   59 
   
    
   
   begin
   
   

   
   60 
   
    data_out_r 
   
   <=
   
    
   
   8
   
   '
   
   b1111_1111;
   
   

   
   61 
   
    data_out_en 
   
   <=
   
    
   
   1
   
   '
   
   b0;
   
   

   
   62 
   
    

   
   63 
   
    
   
   end
   
    

   
   64 
   
    
   
   end
   
   

   
   65 
   
    
   
   else
   
   

   
   66 
   
    
   
   begin
   
   

   
   67 
   
    data_out_r 
   
   <=
   
    
   
   8
   
   '
   
   b1111_1111;
   
   

   
   68 
   
    data_out_en 
   
   <=
   
    
   
   1
   
   '
   
   b0;
   
   

   
   69 
   
    flag 
   
   <=
   
    
   
   4
   
   '
   
   b0000;
   
   

   
   70 
   
    
   
   end
   
    

   
   71 
   
   end
   
   

   
   72 
   
   assign
   
    data_out 
   
   =
   
    data_out_r;

   
   73 
   
   

   
   74 
   
   

   
   75 
   
   reg
   
    [
   
   3
   
   :
   
   0
   
   ] cnt;

   
   76 
   
   reg
   
    clr;

   
   77 
   
   always
   
    @ (
   
   posedge
   
    clk 
   
   or
   
    
   
   negedge
   
    rst_n)

   
   78 
   
   begin
   
   

   
   79 
   
   if
   
    (
   
   !
   
   rst_n)

   
   80 
   
    
   
   begin
   
   

   
   81 
   
    cnt 
   
   <=
   
    
   
   4
   
   '
   
   b0000;
   
   

   
   82 
   
    clr 
   
   <=
   
   1
   
   '
   
   b1;
   
   

   
   83 
   
    
   
   end
   
   

   
   84 
   
   else
   
    
   
   if
   
    (data_out_en) 

   
   85 
   
    cnt 
   
   <=
   
    cnt 
   
   +
   
   1
   
   '
   
   b1;
   
   

   
   86 
   
   else
   
    
   
   if
   
    ((cnt
   
   >=
   
   4
   
   '
   
   d5)&&(cnt<=4
   
   '
   
   d10))

   
   87 
   
    
   
   begin
   
   

   
   88 
   
    cnt
   
   <=
   
   cnt 
   
   +
   
   1
   
   '
   
   b1;
   
   

   
   89 
   
    clr
   
   <=
   
   1
   
   '
   
   b0;
   
   

   
   90 
   
    
   
   end
   
   

   
   91 
   
   else
   
    
   
   if
   
    (cnt
   
   ==
   
   4
   
   '
   
   d11)
   
   

   
   92 
   
    
   
   begin
   
   

   
   93 
   
    cnt 
   
   <=
   
    
   
   4
   
   '
   
   b0000;
   
   

   
   94 
   
    clr 
   
   <=
   
   1
   
   '
   
   b1;
   
   

   
   95 
   
    
   
   end
   
   

   
   96 
   
   end
   
   

   
   97 
   
   

   
   98 
   
   endmodule
   
    
  
  

data_to_reg模块

  
  

   
   
   
    1 
   
   module
   
    data_to_reg

   
    2 
   
   (

   
    3 
   
    clk,

   
    4 
   
    valid,

   
    5 
   
    rst_n,

   
    6 
   
    data,

   
    7 
   
    OUT_A,

   
    8 
   
    OUT_B,

   
    9 
   
    OUT_C,

   
   10 
   
    OUT_D

   
   11 
   
   );

   
   12 
   
   

   
   13 
   
   input
   
    clk;

   
   14 
   
   input
   
    valid;

   
   15 
   
   input
   
    rst_n;

   
   16 
   
   input
   
    [
   
   7
   
   :
   
   0
   
   ] data;

   
   17 
   
   

   
   18 
   
   output
   
    
   
   reg
   
    [
   
   7
   
   :
   
   0
   
   ] OUT_A;

   
   19 
   
   output
   
    
   
   reg
   
    [
   
   7
   
   :
   
   0
   
   ] OUT_B;

   
   20 
   
   output
   
    
   
   reg
   
    [
   
   7
   
   :
   
   0
   
   ] OUT_C;

   
   21 
   
   output
   
    
   
   reg
   
    [
   
   7
   
   :
   
   0
   
   ] OUT_D;

   
   22 
   
   reg
   
    [
   
   2
   
   :
   
   0
   
   ] cnt;

   
   23 
   
   

   
   24 
   
   always
   
    @ (
   
   posedge
   
    clk 
   
   or
   
    
   
   negedge
   
    rst_n)

   
   25 
   
   begin
   
   

   
   26 
   
   if
   
   (
   
   !
   
   rst_n)

   
   27 
   
    cnt 
   
   <=
   
    
   
   3
   
   '
   
   b000;
   
   

   
   28 
   
   else
   
    
   
   if
   
   (valid)

   
   29 
   
    cnt 
   
   <=
   
    cnt 
   
   +
   
   1
   
   '
   
   b1;
   
   

   
   30 
   
   else
   
    
   
   if
   
    (cnt
   
   ==
   
   3
   
   '
   
   d5)
   
   

   
   31 
   
    
   
   begin
   
   

   
   32 
   
    cnt 
   
   <=
   
    
   
   3
   
   '
   
   b000;
   
   

   
   33 
   
    

   
   34 
   
    
   
   end
   
   

   
   35 
   
   end
   
   

   
   36 
   
   

   
   37 
   
   always
   
   @ (
   
   posedge
   
    valid)

   
   38 
   
   begin
   
   

   
   39 
   
    
   
   case
   
    (cnt)

   
   40 
   
    
   
   3
   
   '
   
   d1: 
   
   

   
   41 
   
    
   
   begin
   
    

   
   42 
   
    OUT_A 
   
   <=
   
    data;

   
   43 
   
    
   
   //
   
   OUT_B<=8'b1111_1111;

   
   44 
   
    
   
   //
   
   OUT_C<=8'b1111_1111;

   
   45 
   
    
   
   //
   
   OUT_D<=8'b1111_1111;
   
   

   
   46 
   
    
   
   end
   
   

   
   47 
   
    
   
   3
   
   '
   
   d2: 
   
   

   
   48 
   
    
   
   begin
   
    

   
   49 
   
    
   
   //
   
   OUT_A <= 8'b1111_1111;
   
   

   
   50 
   
    OUT_B
   
   <=
   
   data;

   
   51 
   
    
   
   //
   
   OUT_C<=8'b1111_1111;

   
   52 
   
    
   
   //
   
   OUT_D<=8'b1111_1111;
   
   

   
   53 
   
    
   
   end
   
   

   
   54 
   
    
   
   3
   
   '
   
   d3: 
   
   

   
   55 
   
    
   
   begin
   
    

   
   56 
   
    
   
   //
   
   OUT_A <= 8'b1111_1111;

   
   57 
   
    
   
   //
   
   OUT_B<=8'b1111_1111;
   
   

   
   58 
   
    OUT_C
   
   <=
   
   data;

   
   59 
   
    
   
   //
   
   OUT_D<=8'b1111_1111;
   
   

   
   60 
   
    
   
   end
   
   

   
   61 
   
    
   
   3
   
   '
   
   d4: 
   
   

   
   62 
   
    
   
   begin
   
    

   
   63 
   
    
   
   //
   
   OUT_A <= 8'b1111_1111;

   
   64 
   
    
   
   //
   
   OUT_B<=8'b1111_1111;

   
   65 
   
    
   
   //
   
   OUT_C<=8'b1111_1111;
   
   

   
   66 
   
    OUT_D
   
   <=
   
   data;

   
   67 
   
    
   
   end
   
   

   
   68 
   
    
   
   default
   
   : 

   
   69 
   
    
   
   begin
   
    

   
   70 
   
    OUT_A 
   
   <=
   
    
   
   8
   
   '
   
   b1111_1111;
   
   

   
   71 
   
    OUT_B
   
   <=
   
   8
   
   '
   
   b1111_1111;
   
   

   
   72 
   
    OUT_C
   
   <=
   
   8
   
   '
   
   b1111_1111;
   
   

   
   73 
   
    OUT_D
   
   <=
   
   8
   
   '
   
   b1111_1111;
   
   

   
   74 
   
    
   
   end
   
   

   
   75 
   
    
   
   endcase
   
   

   
   76 
   
   end
   
   

   
   77 
   
   

   
   78 
   
   endmodule