交叉编译生成ARM汇编和反汇编二进制文件生成ARM汇编（指定ARM架构及cpu类型）
1、arm-linux-gcc：
首先编写C程序，假设名字为test.c，保存test.c文件内容：
#include<stdio.h>
int main()
{
printf("hello.world!\n");
return 0;
}
在X86架构下的电脑上生成ARM架构的汇编代码有两种方式：
1、使用交叉编译工具链：arm-linux-gcc，指定-S选项可以生成汇编中间文件。
2、使用arm-linux-objdump反汇编arm二进制文件。
1、arm-linux-gcc：
首先编写C程序，假设名字为test.c，保存test.c文件内容：
#include<stdio.h>
int main()
{
printf("hello.world!\n");
return 0;
}
使用方法如下：
在使用arm-linux-gcc编译C源文件时，使用-S选项可以将C文件（test.c为例）编译到汇编阶段，生成arm汇编代码，使用方式如下：
arm-linux-gcc -march=armv7-a -mtune=cortex-a9 test.c -S -o test.asm
生成arm汇编文件test.asm。
说明：
-march可以指定目标ARM的架构可选参数见（man gcc）
-mtune（类似于-mcpu）可以具体到ARM处理器类型。
注意：
Specifying both -march= and -mcpu= is redundant, and may not in fact have done what you expected in previous compiler versions (maybe even depending on the order in which the arguments were given). The -march switch selects a "generic" ARMv7-A CPU, and -mcpu selects specifically a Cortex-A8 CPU with tuning specific for that core.
Either use "-march=armv7-a -mtune=cortex-a8", or just use "-mcpu=cortex-a8".
Either use "-march=armv7-a -mtune=cortex-a8", or just use "-mcpu=cortex-a8".
所以只用一个-mcpu=cortex-a9也可以
test.asm内容：
1 .arch armv4t
2 .fpu softvfp
3 .eabi_attribute 20, 1
4 .eabi_attribute 21, 1
5 .eabi_attribute 23, 3
6 .eabi_attribute 24, 1
7 .eabi_attribute 25, 1
8 .eabi_attribute 26, 2
9 .eabi_attribute 30, 6
10 .eabi_attribute 18, 4
11 .file "test.c"
12 .section .rodata
13 .align 2
14 .LC0:
15 .ascii "hello.world!\000"
16 .text
17 .align 2
18 .global main
19 .type main, %function
20 main:
21 .fnstart
22 .LFB2:
23 @ Function supports interworking.
24 @ args = 0, pretend = 0, frame = 0
25 @ frame_needed = 1, uses_anonymous_args = 0
26 stmfd sp!, {fp, lr}
27 .save {fp, lr}
28 .LCFI0:
29 .setfp fp, sp, #4
30 add fp, sp, #4
31 .LCFI1:
32 ldr r0, .L3
33 bl puts
34 mov r3, #0
35 mov r0, r3
36 sub sp, fp, #4
36 sub sp, fp, #4
37 ldmfd sp!, {fp, lr}
38 bx lr
39 .L4:
40 .align 2
41 .L3:
42 .word .LC0
43 .LFE2:
44 .fnend
45 .size main, .-main
46 .ident "GCC: (Sourcery G++ Lite 2009q1-176) 4.3.3"
47 .section .note.GNU-stack,"",%progbits
另外，使用arm-linux-objdump 反汇编过程如下：
（1）交叉编译：
arm-linux-gcc test.c -o test ,生成test二进制文件（此处可以加入-O2选项优化代码：
arm-linux-gcc test.c -O2 -o test）
（2）反汇编：
arm-linux-objdump -alD test > test.txt
生成test.txt文件，内容如下：
test: file format elf32-littlearm
test
Disassembly of section .interp:
00008134 <.interp>:
8134: 62696c2f rsbvs r6, r9, #12032 ; 0x2f00
8138: 2d646c2f stclcs 12, cr6, [r4, #-188]!
813c: 756e696c strbvc r6, [lr, #-2412]!
8140: 6f732e78 svcvs 0x00732e78
8144: Address 0x00008144 is out of bounds.
Disassembly of section .note.ABI-tag:
00008148 <.note.ABI-tag>:
8148: 00000004 .word 0x00000004
814c: 00000010 .word 0x00000010
8150: 00000001 .word 0x00000001
8154: 00554e47 .word 0x00554e47
8158: 00000000 .word 0x00000000
815c: 00000002 .word 0x00000002
8160: 00000006 .word 0x00000006
8164: 0000000e .word 0x0000000e
Disassembly of section .hash:
00008168 <.hash>:
8168: 00000003 andeq r0, r0, r3
816c: 00000008 andeq r0, r0, r8
8170: 00000005 andeq r0, r0, r5
8174: 00000006 andeq r0, r0, r6
8178: 00000007 andeq r0, r0, r7
...
8188: 00000002 andeq r0, r0, r2
818c: 00000000 andeq r0, r0, r0
8190: 00000004 andeq r0, r0, r4
8194: 00000003 andeq r0, r0, r3
8198: 00000001 andeq r0, r0, r1
Disassembly of section .dynsym:
0000819c <.dynsym>:
...
81ac: 0000006f andeq r0, r0, pc, rrx
81b0: 00008354 andeq r8, r0, r4, asr r3
81b4: 00000000 andeq r0, r0, r0
81b8: 00000012 andeq r0, r0, r2, lsl r0
81bc: 00000075 andeq r0, r0, r5, ror r0
81c0: 00008360 andeq r8, r0, r0, ror #6
81c4: 00000000 andeq r0, r0, r0
81c8: 00000012 andeq r0, r0, r2, lsl r0
81cc: 0000000f andeq r0, r0, pc
...
81d8: 00000012 andeq r0, r0, r2, lsl r0
81dc: 00000026 andeq r0, r0, r6, lsr #32
...
81e8: 00000020 andeq r0, r0, r0, lsr #32
81ec: 00000035 andeq r0, r0, r5, lsr r0
...
81f8: 00000020 andeq r0, r0, r0, lsr #32
81fc: 0000006a andeq r0, r0, sl, rrx
8200: 00008378 andeq r8, r0, r8, ror r3
8204: 00000000 andeq r0, r0, r0
8208: 00000012 andeq r0, r0, r2, lsl r0
820c: 00000049 andeq r0, r0, r9, asr #32
...
8218: 00000012 andeq r0, r0, r2, lsl r0
Disassembly of section .dynstr:
0000821c <.dynstr>:
821c: 62696c00 rsbvs r6, r9, #0 ; 0x0
8220: 5f636367 svcpl 0x00636367
8224: 6f732e73 svcvs 0x00732e73
8228: 5f00312e svcpl 0x0000312e
822c: 6165615f cmnvs r5, pc, asr r1
8230: 755f6962 ldrbvc r6, [pc, #-2402] ; 78d6 <_init-0xa5a>
8234: 6e69776e cdpvs 7, 6, cr7, cr9, cr14, {3}
8238: 70635f64 rsbvc r5, r3, r4, ror #30
823c: 72705f70 rsbsvc r5, r0, #448 ; 0x1c0
8240: 5f5f0030 svcpl 0x005f0030
8244: 6e6f6d67 cdpvs 13, 6, cr6, cr15, cr7, {3}
8248: 6174735f cmnvs r4, pc, asr r3
824c: 5f5f7472 svcpl 0x005f7472
8250: 764a5f00 strbvc r5, [sl], -r0, lsl #30
8254: 6765525f undefined
8258: 65747369 ldrbvs r7, [r4, #-873]!
825c: 616c4372 smcvs 50226
8260: 73657373 cmnvc r5, #-872415231 ; 0xcc000001
8264: 615f5f00 cmpvs pc, r0, lsl #30
8268: 69626165 stmdbvs r2!, {r0, r2, r5, r6, r8, sp, lr}^
826c: 776e755f undefined
8270: 5f646e69 svcpl 0x00646e69
8274: 5f707063 svcpl 0x00707063
8278: 00317270 eorseq r7, r1, r0, ror r2
827c: 6362696c cmnvs r2, #1769472 ; 0x1b0000
8280: 2e6f732e cdpcs 3, 6, cr7, cr15, cr14, {1}
8284: 75700036 ldrbvc r0, [r0, #-54]!
8288: 61007374 tstvs r0, r4, ror r3
828c: 74726f62 ldrbtvc r6, [r2], #-3938
8290: 6c5f5f00 mrrcvs 15, 0, r5, pc, cr0
8294: 5f636269 svcpl 0x00636269
8298: 72617473 rsbvc r7, r1, #1929379840 ; 0x73000000
829c: 616d5f74 smcvs 54772
82a0: 47006e69 strmi r6, [r0, -r9, ror #28]
82a4: 335f4343 cmpcc pc, #201326593 ; 0xc000001
82a8: 4700352e strmi r3, [r0, -lr, lsr #10]
82ac: 4342494c movtmi r4, #10572 ; 0x294c
82b0: 342e325f strtcc r3, [lr], #-607
...
Disassembly of section .gnu.version:
000082b6 <.gnu.version>:
82b6: 00020000 andeq r0, r2, r0
82ba: 00030002 andeq r0, r3, r2
82be: 00000000 andeq r0, r0, r0
82c2: 00030002 andeq r0, r3, r2
Disassembly of section .gnu.version_r:
000082c8 <.gnu.version_r>:
82c8: 00010001 andeq r0, r1, r1
82cc: 00000001 andeq r0, r0, r1
82d0: 00000010 andeq r0, r0, r0, lsl r0
82d4: 00000020 andeq r0, r0, r0, lsr #32
82d8: 0b792655 bleq 1e51c34 <__bss_end__+0x1e415ac>
82dc: 00030000 andeq r0, r3, r0
82e0: 00000087 andeq r0, r0, r7, lsl #1
82e4: 00000000 andeq r0, r0, r0
82e8: 00010001 andeq r0, r1, r1
82ec: 00000060 andeq r0, r0, r0, rrx
82f0: 00000010 andeq r0, r0, r0, lsl r0
82f4: 00000000 andeq r0, r0, r0
82f8: 0d696914 stcleq 9, cr6, [r9, #-80]!
82fc: 00020000 andeq r0, r2, r0
8300: 0000008f andeq r0, r0, pc, lsl #1
8304: 00000000 andeq r0, r0, r0
Disassembly of section .rel.dyn:
00008308 <.rel.dyn>:
8308: 00010678 andeq r0, r1, r8, ror r6
830c: 00000415 andeq r0, r0, r5, lsl r4
Disassembly of section .rel.plt:
00008310 <.rel.plt>:
8310: 00010668 andeq r0, r1, r8, ror #12
8314: 00000116 andeq r0, r0, r6, lsl r1
8318: 0001066c andeq r0, r1, ip, ror #12
831c: 00000216 andeq r0, r0, r6, lsl r2
8320: 00010670 andeq r0, r1, r0, ror r6
8324: 00000416 andeq r0, r0, r6, lsl r4
8328: 00010674 andeq r0, r1, r4, ror r6
832c: 00000616 andeq r0, r0, r6, lsl r6
Disassembly of section .init:
00008330 <_init>:
_init():
8330: e92d4010 push {r4, lr}
8334: eb000020 bl 83bc <call_gmon_start>
8338: e8bd4010 pop {r4, lr}
833c: e12fff1e bx lr
Disassembly of section .plt:
00008340 <.plt>:
8340: e52de004 push {lr} ; (str lr, [sp, #-4]!)
8344: e59fe004 ldr lr, [pc, #4] ; 8350 <_init+0x20>
8348: e08fe00e add lr, pc, lr
834c: e5bef008 ldr pc, [lr, #8]!
8350: 0000830c .word 0x0000830c
8354: e28fc600 add ip, pc, #0 ; 0x0
8358: e28cca08 add ip, ip, #32768 ; 0x8000
835c: e5bcf30c ldr pc, [ip, #780]!
8360: e28fc600 add ip, pc, #0 ; 0x0
8364: e28cca08 add ip, ip, #32768 ; 0x8000
8368: e5bcf304 ldr pc, [ip, #772]!
836c: e28fc600 add ip, pc, #0 ; 0x0
8370: e28cca08 add ip, ip, #32768 ; 0x8000
8374: e5bcf2fc ldr pc, [ip, #764]!
8378: e28fc600 add ip, pc, #0 ; 0x0
837c: e28cca08 add ip, ip, #32768 ; 0x8000
8380: e5bcf2f4 ldr pc, [ip, #756]!
Disassembly of section .text:
00008384 <_start>:
_start():
8384: e59fc024 ldr ip, [pc, #36] ; 83b0 <_start+0x2c>
8388: e3a0b000 mov fp, #0 ; 0x0
838c: e49d1004 pop {r1} ; (ldr r1, [sp], #4)
8390: e1a0200d mov r2, sp
8394: e52d2004 push {r2} ; (str r2, [sp, #-4]!)
8398: e52d0004 push {r0} ; (str r0, [sp, #-4]!)
839c: e59f0010 ldr r0, [pc, #16] ; 83b4 <_start+0x30>
83a0: e59f3010 ldr r3, [pc, #16] ; 83b8 <_start+0x34>
83a4: e52dc004 push {ip} ; (str ip, [sp, #-4]!)
83a8: ebffffec bl 8360 <_init+0x30>
83ac: ebffffe8 bl 8354 <_init+0x24>
83b0: 00008460 .word 0x00008460
83b4: 00008438 .word 0x00008438
83b8: 00008464 .word 0x00008464
000083bc <call_gmon_start>:
call_gmon_start():
83bc: e59f301c ldr r3, [pc, #28] ; 83e0 <call_gmon_start+0x24>
83c0: e59f201c ldr r2, [pc, #28] ; 83e4 <call_gmon_start+0x28>
83c4: e08f3003 add r3, pc, r3
83c8: e7931002 ldr r1, [r3, r2]
83cc: e3510000 cmp r1, #0 ; 0x0
83d0: e92d4010 push {r4, lr}
83d4: 1bffffe4 blne 836c <_init+0x3c>
83d8: e8bd4010 pop {r4, lr}
83dc: e12fff1e bx lr
83e0: 00008290 .word 0x00008290
83e4: 0000001c .word 0x0000001c
000083e8 <__do_global_dtors_aux>:
__do_global_dtors_aux():
83e8: e59f2010 ldr r2, [pc, #16] ; 8400 <__do_global_dtors_aux+0x18>
83ec: e5d23000 ldrb r3, [r2]
83f0: e3530000 cmp r3, #0 ; 0x0
83f4: 03a03001 moveq r3, #1 ; 0x1
83f8: 05c23000 strbeq r3, [r2]
83fc: e12fff1e bx lr
8400: 00010684 .word 0x00010684
00008404 <frame_dummy>:
frame_dummy():
8404: e59f0024 ldr r0, [pc, #36] ; 8430 <frame_dummy+0x2c>
8408: e5903000 ldr r3, [r0]
840c: e3530000 cmp r3, #0 ; 0x0
8410: e92d4010 push {r4, lr}
8414: 0a000003 beq 8428 <frame_dummy+0x24>
8418: e59f3014 ldr r3, [pc, #20] ; 8434 <frame_dummy+0x30>
841c: e3530000 cmp r3, #0 ; 0x0
8420: 11a0e00f movne lr, pc
8424: 112fff13 bxne r3
8428: e8bd4010 pop {r4, lr}
842c: e12fff1e bx lr
8430: 00010568 .word 0x00010568
8434: 00000000 .word 0x00000000
00008438 <main>:
main():
8438: e92d4800 push {fp, lr}
843c: e28db004 add fp, sp, #4 ; 0x4
8440: e59f0014 ldr r0, [pc, #20] ; 845c <main+0x24>
8444: ebffffcb bl 8378 <_init+0x48>
8448: e3a03000 mov r3, #0 ; 0x0
844c: e1a00003 mov r0, r3
8450: e24bd004 sub sp, fp, #4 ; 0x4
8454: e8bd4800 pop {fp, lr}
8458: e12fff1e bx lr
845c: 000084e8 .word 0x000084e8
00008460 <__libc_csu_fini>:
__libc_csu_fini():
8460: e12fff1e bx lr
00008464 <__libc_csu_init>:
__libc_csu_init():
8464: e92d47f0 push {r4, r5, r6, r7, r8, r9, sl, lr}
8468: e1a08001 mov r8, r1
846c: e1a07002 mov r7, r2
8470: e1a0a000 mov sl, r0
8474: ebffffad bl 8330 <_init>
8478: e59f104c ldr r1, [pc, #76] ; 84cc <__libc_csu_init+0x68>
847c: e59f304c ldr r3, [pc, #76] ; 84d0 <__libc_csu_init+0x6c>
8480: e59f204c ldr r2, [pc, #76] ; 84d4 <__libc_csu_init+0x70>
8484: e0613003 rsb r3, r1, r3
8488: e08f2002 add r2, pc, r2
848c: e1b05143 asrs r5, r3, #2
8490: e0822001 add r2, r2, r1
8494: 0a00000a beq 84c4 <__libc_csu_init+0x60>
8498: e1a06002 mov r6, r2
849c: e3a04000 mov r4, #0 ; 0x0
84a0: e1a0000a mov r0, sl
84a4: e1a01008 mov r1, r8
84a8: e1a02007 mov r2, r7
84ac: e796c104 ldr ip, [r6, r4, lsl #2]
84b0: e1a0e00f mov lr, pc
84b4: e12fff1c bx ip
84b8: e2844001 add r4, r4, #1 ; 0x1
84bc: e1540005 cmp r4, r5
84c0: 3afffff6 bcc 84a0 <__libc_csu_init+0x3c>
84c4: e8bd47f0 pop {r4, r5, r6, r7, r8, r9, sl, lr}
84c8: e12fff1e bx lr
84cc: ffffff04 .word 0xffffff04
84d0: ffffff08 .word 0xffffff08
84d4: 000081cc .word 0x000081cc
Disassembly of section .fini:
000084d8 <_fini>:
_fini():
84d8: e92d4010 push {r4, lr}
84dc: e8bd4010 pop {r4, lr}
84e0: e12fff1e bx lr
Disassembly of section .rodata:
000084e4 <_IO_stdin_used>:
84e4: 00020001 .word 0x00020001
84e8: 6c6c6568 .word 0x6c6c6568
84ec: 6f772e6f .word 0x6f772e6f
84f0: 21646c72 .word 0x21646c72
84f4: 00000000 .word 0x00000000
Disassembly of section .ARM.extab:
000084f8 <.ARM.extab>:
84f8: 81019b40 .word 0x81019b40
84fc: 8480b0b0 .word 0x8480b0b0
8500: 00000000 .word 0x00000000
Disassembly of section .ARM.exidx:
00008504 <.ARM.exidx>:
8504: 7fff7afc .word 0x7fff7afc
8508: 80b0b0b0 .word 0x80b0b0b0
850c: 7ffffe34 .word 0x7ffffe34
8510: 00000001 .word 0x00000001
8514: 7ffffea8 .word 0x7ffffea8
8518: 80a8b0b0 .word 0x80a8b0b0
851c: 7ffffecc .word 0x7ffffecc
8520: 80b0b0b0 .word 0x80b0b0b0
8524: 7ffffee0 .word 0x7ffffee0
8528: 80a8b0b0 .word 0x80a8b0b0
852c: 7fffff0c .word 0x7fffff0c
8530: 7fffffc8 .word 0x7fffffc8
8534: 7fffff2c .word 0x7fffff2c
8538: 80b0b0b0 .word 0x80b0b0b0
853c: 7fffff28 .word 0x7fffff28
8540: 80aeb0b0 .word 0x80aeb0b0
8544: 7fffff94 .word 0x7fffff94
8548: 00000001 .word 0x00000001
854c: 7fff7ab4 .word 0x7fff7ab4
8550: 80b0b0b0 .word 0x80b0b0b0
8554: 7fffff90 .word 0x7fffff90
8558: 00000001 .word 0x00000001
Disassembly of section .eh_frame:
0000855c <__FRAME_END__>:
855c: 00000000 .word 0x00000000
Disassembly of section .init_array:
00010560 <__frame_dummy_init_array_entry>:
__init_array_start():
10560: 00008404 .word 0x00008404
Disassembly of section .fini_array:
00010564 <__do_global_dtors_aux_fini_array_entry>:
10564: 000083e8 .word 0x000083e8
Disassembly of section .jcr:
00010568 <__JCR_END__>:
10568: 00000000 .word 0x00000000
Disassembly of section .dynamic:
0001056c <_DYNAMIC>:
1056c: 00000001 andeq r0, r0, r1
10570: 00000001 andeq r0, r0, r1
10574: 00000001 andeq r0, r0, r1
10578: 00000060 andeq r0, r0, r0, rrx
1057c: 0000000c andeq r0, r0, ip
10580: 00008330 andeq r8, r0, r0, lsr r3
10584: 0000000d andeq r0, r0, sp
10588: 000084d8 ldrdeq r8, [r0], -r8
1058c: 00000019 andeq r0, r0, r9, lsl r0
10590: 00010560 andeq r0, r1, r0, ror #10
10594: 0000001b andeq r0, r0, fp, lsl r0
10598: 00000004 andeq r0, r0, r4
1059c: 0000001a andeq r0, r0, sl, lsl r0
105a0: 00010564 andeq r0, r1, r4, ror #10
105a4: 0000001c andeq r0, r0, ip, lsl r0
105a8: 00000004 andeq r0, r0, r4
105ac: 00000004 andeq r0, r0, r4
105b0: 00008168 andeq r8, r0, r8, ror #2
105b4: 00000005 andeq r0, r0, r5
105b8: 0000821c andeq r8, r0, ip, lsl r2
105bc: 00000006 andeq r0, r0, r6
105c0: 0000819c muleq r0, ip, r1
105c4: 0000000a andeq r0, r0, sl
105c8: 00000099 muleq r0, r9, r0
105cc: 0000000b andeq r0, r0, fp
105d0: 00000010 andeq r0, r0, r0, lsl r0
105d4: 00000015 andeq r0, r0, r5, lsl r0
105d8: 00000000 andeq r0, r0, r0
105dc: 00000003 andeq r0, r0, r3
105e0: 0001065c andeq r0, r1, ip, asr r6
105e4: 00000002 andeq r0, r0, r2
105e8: 00000020 andeq r0, r0, r0, lsr #32
105ec: 00000014 andeq r0, r0, r4, lsl r0
105f0: 00000011 andeq r0, r0, r1, lsl r0
105f4: 00000017 andeq r0, r0, r7, lsl r0
105f8: 00008310 andeq r8, r0, r0, lsl r3
105fc: 00000011 andeq r0, r0, r1, lsl r0
10600: 00008308 andeq r8, r0, r8, lsl #6
10604: 00000012 andeq r0, r0, r2, lsl r0
10608: 00000008 andeq r0, r0, r8
1060c: 00000013 andeq r0, r0, r3, lsl r0
10610: 00000008 andeq r0, r0, r8
10614: 6ffffffe svcvs 0x00fffffe
10618: 000082c8 andeq r8, r0, r8, asr #5
1061c: 6fffffff svcvs 0x00ffffff
10620: 00000002 andeq r0, r0, r2
10624: 6ffffff0 svcvs 0x00fffff0
10628: 000082b6 strheq r8, [r0], -r6
...
Disassembly of section .got:
0001065c <_GLOBAL_OFFSET_TABLE_>:
1065c: 0001056c andeq r0, r1, ip, ror #10
...
10668: 00008340 andeq r8, r0, r0, asr #6
1066c: 00008340 andeq r8, r0, r0, asr #6
10670: 00008340 andeq r8, r0, r0, asr #6
10674: 00008340 andeq r8, r0, r0, asr #6
10678: 00000000 andeq r0, r0, r0
Disassembly of section .data:
0001067c <__data_start>:
__data_start():
1067c: 00000000 .word 0x00000000
00010680 <__dso_handle>:
10680: 00000000 .word 0x00000000
Disassembly of section .bss:
00010684 <completed.5903>:
10684: 00000000 andeq r0, r0, r0
Disassembly of section .ARM.attributes:
00000000 <.ARM.attributes>:
0: 00002541 andeq r2, r0, r1, asr #10
4: 61656100 cmnvs r5, r0, lsl #2
8: 01006962 tsteq r0, r2, ror #18
c: 0000001b andeq r0, r0, fp, lsl r0
10: 00543405 subseq r3, r4, r5, lsl #8
14: 01080206 tsteq r8, r6, lsl #4
18: 04120109 ldreq r0, [r2], #-265
1c: 01150114 tsteq r5, r4, lsl r1
20: 01180317 tsteq r8, r7, lsl r3
24: Address 0x00000024 is out of bounds.
Disassembly of section .comment:
00000000 <.comment>:
0: 43434700 movtmi r4, #14080 ; 0x3700
4: 5328203a teqpl r8, #58 ; 0x3a
8: 6372756f cmnvs r2, #465567744 ; 0x1bc00000
c: 20797265 rsbscs r7, r9, r5, ror #4
10: 202b2b47 eorcs r2, fp, r7, asr #22
14: 6574694c ldrbvs r6, [r4, #-2380]!
18: 30303220 eorscc r3, r0, r0, lsr #4
1c: 2d317139 ldfcss f7, [r1, #-228]!
20: 29363731 ldmdbcs r6!, {r0, r4, r5, r8, r9, sl, ip, sp}
24: 332e3420 teqcc lr, #536870912 ; 0x20000000
28: Address 0x00000028 is out of bounds.
Disassembly of section .debug_frame:
00000000 <.debug_frame>:
0: 0000000c andeq r0, r0, ip
4: ffffffff undefined instruction 0xffffffff
8: 7c010001 stcvc 0, cr0, [r1], {1}
c: 000d0c0e andeq r0, sp, lr, lsl #24
10: 0000000c andeq r0, r0, ip
14: 00000000 andeq r0, r0, r0
18: 00008460 andeq r8, r0, r0, ror #8
1c: 00000004 andeq r0, r0, r4
20: 00000020 andeq r0, r0, r0, lsr #32
24: 00000000 andeq r0, r0, r0
28: 00008464 andeq r8, r0, r4, ror #8
2c: 00000074 andeq r0, r0, r4, ror r0
30: 8e200e44 cdphi 14, 2, cr0, cr0, cr4, {2}
34: 89028a01 stmdbhi r2, {r0, r9, fp, pc}
38: 87048803 strhi r8, [r4, -r3, lsl #16]
3c: 85068605 strhi r8, [r6, #-1541]
40: 00088407 andeq r8, r8, r7, lsl #8
解释：第一列是段地址与段偏移，第二列是指令操作码，对应ARM指令手册（ARM Architecture Reference Manual）可以看到
对比使用-S选项生成的test.asm和反汇编生成的test.txt的区别为：
（1）反汇编可以生成ARM指令操作码，-S生成的汇编没有指令码
（2）反汇编的代码是经过编译器优化过的。
（3）反汇编代码量很大。