Windows 下使用icuras+GRKWave

使用开源的verilog在windows下对verilog代码进行仿真。

开源的icuras verilog和GRKWave仿真器下载地址：

http://bleyer.org/icarus/

不过在安装icuras中会提示是否安装GRKWave,当然了，这就不用下GRKWave了。

下面测试一下软件是否可用了：

代码使用的是UC Berkeley EECS150: Finite State Machines in Verilog中出现的一个有限自动机的代码

 BasicFSM.v 

module BasicFsm (
 // ------------------------------------------------------------
 // Inputs
 // ------------------------------------------------------------
 input wire Clock ,
 input wire Reset ,
 input wire A,
 input wire B,
 // ------------------------------------------------------------

 // ------------------------------------------------------------
 // Outputs
 // ------------------------------------------------------------
 output wire Output1 ,
 output wire Output2 ,
 output reg [2:0] Status
 // ------------------------------------------------------------
 );

 // --------------------------------------------------------------------
 // State Encoding
 // --------------------------------------------------------------------
 localparam 	STATE_Initial = 3'd0 ,
 		STATE_1 = 3'd1 ,
		STATE_2 = 3'd2 ,
 		STATE_3 = 3'd3 ,
 		STATE_4 = 3'd4 ,
 		STATE_5_PlaceHolder = 3'd5 ,
 		STATE_6_PlaceHolder = 3'd6 ,
 		STATE_7_PlaceHolder = 3'd7;
 // --------------------------------------------------------------------

// --------------------------------------------------------------------
 // State reg Declarations
 // --------------------------------------------------------------------
 reg [2:0] CurrentState ;
 reg [2:0] NextState ;
 // --------------------------------------------------------------------

 // --------------------------------------------------------------------
 // Outputs
 // --------------------------------------------------------------------
 // 1- bit outputs
 assign Output1 = ( CurrentState == STATE_1 ) | ( CurrentState == STATE_2 );
 assign Output2 = ( CurrentState == STATE_2 );

 // multi - bit outputs
 always@ ( * ) begin
 	Status = 3'b000 ;
 	case ( CurrentState )
 		STATE_2 : begin
 			Status = 3'b010 ;
 		end
 		STATE_3 : begin
 			Status = 3'b011 ;
 		end
 	endcase
 end
 // --------------------------------------------------------------------
 // Synchronous State - Transition always@ ( posedge Clock ) block
 // --------------------------------------------------------------------
 always@ ( posedge Clock ) begin
 	if ( Reset ) CurrentState <= STATE_Initial ;
 	else CurrentState <= NextState ;
 end
 // --------------------------------------------------------------------

 // --------------------------------------------------------------------
 // Conditional State - Transition always@ ( * ) block
 // --------------------------------------------------------------------
 
 //always@ ( * ) begin
 always@ ( CurrentState ) begin
 	NextState = CurrentState ;
	case ( CurrentState )
 		STATE_Initial : begin
 			NextState = STATE_1 ;
 		end
 		STATE_1 : begin
 			if (A & B) NextState = STATE_2 ;
 		end
 		STATE_2 : begin
 			if (A) NextState = STATE_3 ;
 		end
 		STATE_3 : begin
 			if (!A & B) NextState = STATE_Initial ;
 			else if (A & !B) NextState = STATE_4 ;
 		end
 		STATE_4 : begin
 		end
 		STATE_5_PlaceHolder : begin
 			NextState = STATE_Initial ;
 		end
 		STATE_6_PlaceHolder : begin
 			NextState = STATE_Initial ;
 		end
 		STATE_7_PlaceHolder : begin
 			NextState = STATE_Initial ;
 		end
 	endcase
 end
 // --------------------------------------------------------------------

 endmodule
 // --------------------------------------------------------------------

下面是我加的Testbench代码：

 

module FSM_tb; 

   reg Clock;
   reg Reset;
   reg A;
   reg B;

   wire Output1;
   wire Output2;
   wire [2:0] Status;

   initial 
     begin 
        $dumpfile("FSM.vcd"); 
        $dumpvars(0, fsm); 
        $monitor("Output1: %b,Output2: %b,Status: %b", Output1,Output2,Status); 
        Clock = 0;
	Reset = 0;
     	A = 0;
	B = 0;
        #140 $finish; 
     end

   always
	#5 Clock = !Clock; 

   initial
     begin
	#  3 Reset =1;
	#  4 Reset =0;
	#116 Reset =1;
     end
    
   initial
     begin
	#33  A =1;
	#10  A =0;
	#10  A =1;
	#10  A =0;
	#30  A =1;
     end
   initial
     begin
	#32  B =1;
	#30  B =0;
	#10  B =1;
	#40  B =0;
     end
  
   BasicFsm fsm(Clock,Reset,A,B,Output1,Output2,Status);

endmodule 

下面编译代码并查看波形：

但执行完gtkwave FSM.vcd后GRKWave被调用，将左下栏的信号投到Signals栏中：

 

此状态机是Moore机，输出只依赖与当前状态（Clock时钟信号的沿变化触发CurrentState，而CurrentState的变化有触发了当前状态的输出，所以一个很好的结论：Moore机的输出同步与时钟Clock，避免了setup timing violations）.下一状态与当前状态和输入有关，从图中标记可看出当当前状态CurrentState为1时，A=1，B=1使得下一状态NextState变为了2, 前面说了当前状态同步CurrentState与Clock，而输入信号可能是任意时刻变化的，所以下一状态NextState并不同步与Clock。

 

"EECS150: Finite State Machines in Verilog“在http://www-inst.eecs.berkeley.edu/~cs150/Documents/FSM.pdf