深入理解ARM体系架构（S3C6410）---系统时钟初始化实例

本文章由muge0913编写，转载请注明出处：http://blog.csdn.net/muge0913/article/details/7428083

作者：张同浩，邮箱：[email protected]

关于这篇文章：

1、此段程序实现了533M的系统时钟设置。关于s3c6410时钟知识请看另一篇文章：http://blog.csdn.net/muge0913/article/details/7364706

2、用的开发工具为RVDS2.2。写这篇文章主要是为下篇的sdram初始化和代码拷贝实现，做个知识的铺垫。呵呵

3、如果要实现其他频率的设置，在下面的 定义数据代码 中修改相应的数据即可，主要是分频值的设置。

程序如下：

1、定义数据：

;clock
ELFIN_WATCHDOG_BASE  EQU   0x7e004000
ELFIN_CLOCK_POWER_BASE EQU   0x7e00f000
OTHERS_OFFSET   	EQU   0x900
APLL_LOCK_OFFSET  	EQU   0x00
MPLL_LOCK_OFFSET  	EQU   0x04
EPLL_LOCK_OFFSET  	EQU   0x08
CLK_DIV2_OFFSET   	EQU   0x28
CLK_DIV0_OFFSET   	EQU   0x20
Startup_PCLKdiv   	EQU   3
Startup_HCLKx2div  	EQU   1
Startup_HCLKdiv   	EQU   1
Startup_MPLLdiv   	EQU   1
Startup_APLLdiv   	EQU   1
CLK_DIV_VAL   		EQU   ((Startup_PCLKdiv<<12)|(Startup_HCLKx2div<<9)|(Startup_HCLKdiv<<8)|(Startup_MPLLdiv<<4)|Startup_APLLdiv)
APLL_MDIV   		EQU   266
APLL_PDIV   		EQU   3
APLL_SDIV   		EQU   1
APLL_VAL   			EQU   ((1<<31 | APLL_MDIV<<16 | APLL_PDIV<<8 | APLL_SDIV))
APLL_CON_OFFSET  	EQU   0x0c
MPLL_CON_OFFSET  	EQU   0x10
EPLL_CON0_OFFSET  	EQU   0x14
EPLL_CON1_OFFSET  	EQU   0x18
CLK_SRC_OFFSET  	EQU   0x1c
MPLL_MDIV   		EQU   266
MPLL_PDIV   		EQU   3
MPLL_SDIV   		EQU   1
MPLL_VAL   			EQU   ((1<<31 | MPLL_MDIV<<16 | MPLL_PDIV<<8 | MPLL_SDIV))

2、时钟初始化程序：

clk_init
	ldr r0, =ELFIN_CLOCK_POWER_BASE ;0x7e00f000
	 ldr r1, [r0, #OTHERS_OFFSET]
	 mov r2, #0x40
	 orr r1, r1, r2
	 str r1, [r0, #OTHERS_OFFSET]
	 nop
	 nop
	 nop
	 nop
	 nop
	 ldr r2, =0x80
	 orr r1, r1, r2
	 str r1, [r0, #OTHERS_OFFSET]
check_syncack
	 ldr r1, [r0, #OTHERS_OFFSET]
	 ldr r2, =0xf00
	 and r1, r1, r2
	 cmp r1, #0xf00
	 bne check_syncack
	 mov r1, #0xff00
	 orr r1, r1, #0xff
	 str r1, [r0, #APLL_LOCK_OFFSET]
	 str r1, [r0, #MPLL_LOCK_OFFSET]
	 str r1, [r0, #EPLL_LOCK_OFFSET]
	 ldr    r1, [r0, #CLK_DIV2_OFFSET]
	 bic r1, r1, #0x70000
	 orr r1, r1, #0x30000
	 str r1, [r0, #CLK_DIV2_OFFSET]
	 ldr    r1, [r0, #CLK_DIV0_OFFSET] ;Set Clock Divider
	 bic r1, r1, #0x30000
	 bic r1, r1, #0xff00
	 bic r1, r1, #0xff
	 ldr r2, =CLK_DIV_VAL
	 orr r1, r1, r2
	 str r1, [r0, #CLK_DIV0_OFFSET]
	 ldr r1, =APLL_VAL
	 str r1, [r0, #APLL_CON_OFFSET]
	 ldr r1, =MPLL_VAL
	 str r1, [r0, #MPLL_CON_OFFSET]
	 ldr r1, =0x80200203   ;FOUT of EPLL is 96MHz
	 str r1, [r0, #EPLL_CON0_OFFSET]
	 ldr r1, =0x0
	 str r1, [r0, #EPLL_CON1_OFFSET]
	 ldr r1, [r0, #CLK_SRC_OFFSET] ;APLL, MPLL, EPLL select to Fout
	 ldr r2, =0x2007
	 orr r1, r1, r2
	 str r1, [r0, #CLK_SRC_OFFSET]
	 ;wait at least 200us to stablize all clock
	 mov r1, #0x10000
1 
	subs r1, r1, #1
	 bne %B1
	 ;Synchronization for VIC port
	 ldr r1, [r0, #OTHERS_OFFSET]
	 orr r1, r1, #0x20
	 str r1, [r0, #OTHERS_OFFSET]

	 mov pc,lr