首先编写一个counter.v的文件,如下:
module counter(out, clk, reset); parameter WIDTH = 8; output [WIDTH-1 : 0] out; input clk, reset; reg [WIDTH-1 :0 ] out; wire clk, reset; always @(posedge clk) out <= out + 1; always @reset if (reset) assign out = 0; else deassign out; endmodule //counter
`timescale 1ns/1ns module test; /*Make a reset that pulses once.*/ reg reset = 0; initial begin #17 reset = 1; #11 reset = 0; #29 reset = 1; #11 reset = 0; #100 $stop; end /*Make a regular pulsing closk*/ reg clk = 0; always #5 clk = !clk; wire [7:0] value; counter c1 (value, clk, reset); initial $monitor("At time %t, value = %h (%0d)",$time, value, value); endmodule //test
** Continue **
这里要是没有finish的命令,vvp会一直运行,如果用下面的语句:
>vvp -n mydesign
G:\Verilog HDL\iverilog\Demo\counter>vvp -n mydesign
At time 0, value = xx (x)
At time 17, value = 00 (0)
At time 35, value = 01 (1)
At time 45, value = 02 (2)
At time 55, value = 03 (3)
At time 57, value = 00 (0)
At time 75, value = 01 (1)
At time 85, value = 02 (2)
At time 95, value = 03 (3)
At time 105, value = 04 (4)
At time 115, value = 05 (5)
At time 125, value = 06 (6)
At time 135, value = 07 (7)
At time 145, value = 08 (8)
At time 155, value = 09 (9)
At time 165, value = 0a (10)
G:\Verilog HDL\iverilog\Demo\counter>
这样就避免了上面的尴尬局面,不过以后还要继续学习vvp。