完事应该可以编译成功,脚本如下(bspbuild.sh):
1 #!/bin/bash
2
3 export RTEMS_ROOT=/home/wang2/codePrj/ldd/sources/rtems-4.11
4 export LIBBSB=/home/wang2/codePrj/ldd/sources/rtems-4.11/c/src/lib/libbsp
5
6 echo ${PWD}
7
8 # pre-config
9 cd ${RTEMS_ROOT}
10 ./bootstrap -c
11 ./bootstrap -p
12 ./bootstrap
13
14 # Configure
15 cd ${RTEMS_ROOT}/build/mini2440
16 rm -rf ./*
17
18 ../../configure --target=arm-rtemseabi4.11 --enable-posix \
19 --disable-cxx --disable-itron --enable-networking \
20 --enable-tests=samples \
21 --enable-rtemsbsp=mini2440
--target:是告诉configure编译器是arm-rtemseabi4.11-xxx工具链;/* What is the input clock freq in hertz?
* FCLK:HCLK:PCLK = 1:4:8
* FCLK = 405MHz
*/
#define BSP_OSC_FREQ 12000000 /* 12 MHz oscillator */
#define M_MDIV 0x7f /* FCLK=405Mhz, origin: 81, to: 0x7f*/
#define M_PDIV 2
#define M_SDIV 1
#define M_CLKDIVN 5 /* HCLK=FCLK/4, PCLK=FCLK/2 */
// 2 to 5
#define REFEN 0x1 /* enable refresh */
#define TREFMD 0x0 /* CBR(CAS before RAS)/auto refresh */
#define Trp 0x0 /* 2 clk */
#define Trc 0x3 /* 7 clk */
#define Tchr 0x2 /* 3 clk */
7.1.2. 时钟:2440和2410的PLL计算公式不太一样,get_FCLK()函数:
return((BSP_OSC_FREQ * m) / (p << s));
改成
return((BSP_OSC_FREQ * m * 2) / (p << s));
7.1.3. 在support.c中:
/* return HCLK frequency */
uint32_t get_HCLK(void)
{
if (rCLKDIVN & 0x2)
return get_FCLK()/2;
else
return get_FCLK();
}
改成
/* return HCLK frequency */
uint32_t get_HCLK(void)
{
if ((rCLKDIVN & 0x06) == 0x04)
return get_FCLK() / 4;
else if ((rCLKDIVN & 0x06) == 0x00)
return get_FCLK();
else if ((rCLKDIVN & 0x06) == 0x02)
return get_FCLK() / 2;
else
return get_FCLK() / 3;
}
7.2. sdram刷新设置/* setup rREFRESH
* period = 15.6 us, HCLK=66Mhz, (2048+1-15.6*66)
*/
REFCNT = 2048+1-(15.6*get_HCLK()/1000000);
rREFRESH = ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT);
/* set prescaler for timers 2,3,4 to 16(15+1) */
cr = rTCFG0 & 0xFFFF00FF;
rTCFG0 = (cr | (15<<8));
/* set prescaler for timers 0,1 to 1(0+1) */
cr = rTCFG0 & 0xFFFFFF00;
rTCFG0 = (cr | (0<<0));
其中,mini2440外接MT48LC16M16A2的刷新周期为64ms/8k,即7.8125us;
REFCNT = 2048 + 1 - (7.8125 * get_HCLK() / 1000000);
rGPHCON |= 0xa0;
rGPHUP = 0x0c;
使用不带FIFO模式:
/* FIFO disable, Tx/Rx FIFO clear */
rUFCON0 = 0x0;
rUMCON0 = 0x0;
rUCON0 = 0x245;
改成
rUCON0 = 0x05;/* normal; rx: int or poll; no int when error occured and timeout; rx: edge; tx: int or poll; edge; clock: PCLK */
static ssize_t uart_write(int minor, const char *buf, size_t len)中, /* Wait for fifo to have room */ while(!(rUTRSTAT0 & 0x2)) { continue; }改成
while(!(rUTRSTAT0 & 0x4)) { continue; }
MEMORY { SDRAM_MMU : ORIGIN = 0x30000000, LENGTH = 16k // TLB SDRAM : ORIGIN = 0x30004000, LENGTH = 64M_16k }改成
MEMORY { SDRAM : ORIGIN = 0x30000000, LENGTH = 64M - 16k SDRAM_MMU : ORIGIN = 0x33ffc000, LENGTH = 16k }9. compile
10. 无图无真相
By liitokala