状态机与非状态机

Quartus 9.1 手册：
Synthesis tools can recognize and encode Verilog HDL and VHDL state machines
during synthesis. This section presents guidelines to ensure the best results when you
use state machines. Ensuring that your synthesis tool recognizes a piece of code as a
state machine allows the tool to recode the state variables to improve the quality of
results, and allows the tool to use the known properties of state machines to optimize
other parts of the design. When synthesis recognizes a state machine, it is often able to
improve the design area and performance.
To achieve the best results on average, synthesis tools often use one-hot encoding for
FPGA devices and minimal-bit encoding for CPLD devices, although the choice of
implementation can vary for different state machines and different devices. Refer to
your synthesis tool documentation for specific ways to control the manner in which
state machines are encoded.
To ensure proper recognition and inference of state machines and to improve the
quality of results, Altera recommends that you observe the following guidelines,
which apply to both Verilog HDL and VHDL:
    ■ Assign default values to outputs derived from the state machine so that synthesis
    does not generate unwanted latches.
    ■ Separate the state machine logic from all arithmetic functions and data paths,
    including assigning output values.
    ■ If your design contains an operation that is used by more than one state, define the
    operation outside the state machine and cause the output logic of the state
    machine to use this value.
    ■ Use a simple asynchronous or synchronous reset to ensure a defined power-up
    state. If your state machine design contains more elaborate reset logic, such as both
    an asynchronous reset and an asynchronous load, the Quartus II software
    generates regular logic rather than inferring a state machine.
If a state machine enters an illegal state due to a problem with the device, the design
likely ceases to function correctly until the next reset of the state machine. Synthesis
tools do not provide for this situation by default. The same issue applies to any other
registers if there is some kind of fault in the system. A default or when others
clause does not affect this operation, assuming that your design never deliberately
enters this state. Synthesis tools remove any logic generated by a default state if it is
not reachable by normal state machine operation.
Many synthesis tools (including Quartus II integrated synthesis) have an option to
implement a safe state machine. The software inserts extra logic to detect an illegal
state and force the state machine’s transition to the reset state. It is commonly used
when the state machine can enter an illegal state. The most common cause of this
situation is a state machine that has control inputs that come from another clock
domain, such as the control logic for a dual-clock FIFO
This option protects only state machines by forcing them into the reset state. All other
registers in the design are not protected this way. If the design has asynchronous
inputs, Altera recommends using a synchronization register chain instead of relying
on the safe state machine option.

To ensure proper recognition and inference of Verilog HDL state machines, observe
the following additional Verilog HDL guidelines. Some of these guidelines may be
specific to Quartus II integrated synthesis. Refer to your synthesis tool documentation
for specific coding recommendations.
If the state machine is not recognized and inferred by the synthesis software (such as
Quartus II integrated synthesis), the state machine is implemented as regular logic
gates and registers and the state machine is not listed as a state machine in the
Analysis & Synthesis section of the Quartus II Compilation Report. In this case, the
software does not perform any of the optimizations that are specific to state machines.
■ No state machine is inferred in the Quartus II software if the state transition logic
    uses arithmetic similar to that shown in the following example:
                case (state)
                    0: begin
                        if (ena) next_state <= state + 2;
                        else next_state <= state + 1;
                    end
                    1: begin
                    ...
                endcase
■ No state machine is inferred in the Quartus II software if the state variable is an
output.
■ No state machine is inferred in the Quartus II software for signed variables.

可以在Signal Tab II中观察是否被综合成状态机
非状态机
状态机