Peripheral Port Memory Remap Register
1、今天在看三星的uboot-1.1.6（s3c6410）的源码，start.s文件时，看到一段代码，如下所示：
/* Peri port setup */
ldr r0, =0x70000000
orr r0, r0, #0x13
mcr p15,0,r0,c15,c2,4 @ 256M(0x70000000-0x7fffffff)
当时很疑惑，不知道这段代码有什么用，经过一番查找，原来和ARM的协处理器有关，如下所示：
c15, Peripheral Port Memory Remap Register。
2、c15, Peripheral Port Memory Remap Register ----- 摘于ARM1176手册
The purpose of the Peripheral Port Memory Remap Register is to remap the memory attributes to Non-Shared Device. This forces access to the peripheral port and overrides what is programmed in the page tables. The remapping happens both with the MMU enabled and with the MMU disabled, therefore you can remap the peripheral port even when you do not use the MMU. The Peripheral Port Memory Remap Register has the highest priority, higher than that of the Primary and Normal memory remap registers.
Table 3.132 lists the purposes of the individual bits in the Peripheral Port Memory Remap Register.
The Peripheral Port Memory Remap Register is:
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in CP15 c15
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a 32-bit read/write register banked for Secure and Non-secure worlds
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accessible in privileged modes only.
Figure 3.71 shows the arrangement of the bits in the register.
Figure 3.71. Peripheral Port Memory Remap Register format
Table 3.132 lists how the bit values correspond with the functions of the Peripheral Port Memory Remap Register.
Table 3.132. Peripheral Port Memory Remap Register bit functions
Attempts to write to this register in Secure Privileged mode when CP15SDISABLE is HIGH result in an Undefined exception, see TrustZone write access disable.
Table 3.133 lists the results of attempted access for each mode.
Table 3.133. Results of access to the Peripheral Port Remap Register
To use the memory remap registers read or write CP15 with:
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Opcode_1 set to 0
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CRn set to c15
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CRm set to c2
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Opcode_2 set to 4.
For example:
MRC p15, 0, <Rd>, c15, c2, 4 ; Read Peripheral Port Memory Remap Register
MCR p15, 0, <Rd>, c15, c2, 4 ; Write Peripheral Port Memory Remap Register
3、Using the Peripheral Port Memory Remap Register -----摘于ARM1173手册You use this register to remap the peripheral port.
The peripheral port is accessed by memory locations whose page table attributes are Non-Shared Device. You can program a region of memory to be remapped to being Non-Shared Device while the MMU is disabled to provide access to the peripheral port when the MMU is disabled. In addition, the same mechanism will override the page table entries, providing an additional mechanism for accessing the peripheral port. This mechanism is suitable for operating systems where access to the page table formats is not readily available.
The use of the remapping of the peripheral port will change the memory region used for those memory locations that are remapped to be Non-Shared Device, regardless of what has been programmed in the page tables.
If the region of memory mapped by this mechanism overlaps with the regions of memory that are contained within the TCMs not marked as SmartCache, then the memory locations that are mapped as both TCM and Non-Shared Device are treated as TCM. Therefore, the overlapping region does not access the peripheral port.
If the region of memory mapped by this mechanism overlaps with the regions of memory that are contained within the TCMs marked as SmartCache, then the memory locations that are mapped as both TCM and Non-Shared Device are treated as Non-Shared Device, and the SmartCache functionality is not used enabled for those addresses.
The peripheral port is only used by data accesses. Unaligned accesses and exclusive accesses are not supported by the peripheral port (because they are not supported in Device memory), and attempting to perform such accesses has Unpredictable results when using the peripheral port as a result of the Peripheral Port Memory Remap Register.
Any remapping on Non-Shared Device memory by the Data Memory Remap Register has no effect on regions mapped to Non-Shared Device by the Peripheral Port Memory Remap Register.
To entirely disable the peripheral port, the Peripheral Port Memory Remap Register must be programmed to 0 size and page table entries of type Non-Shared Device must be avoided.