Verilog (二) multiplexer and decoder

1  mutiplexer 数据选择器

1)  one-bit wide 2-1 mux

wire  dout  = sel? din1 : din0;  // conditional continuous and wire assignment

2)  4-1 mux

module  mux4_1(sel, din0, din1, din2, din3, dout);
  input  [1:0]  sel;
  input    din0, din1, din2, din3;
  output  dout;
  reg   dout;

always @ (sel or din0 or din1 or din2 or din3)
begin
  case(sel)
    2'b00:  dout = din0;
    2'b01:  dout = din1;
    2'b10:  dout = din2;
    2'b11:  dout = din3;
    default:  dout = din0;
  endcase
end

endmodule
mux4_1

3)  two-bit wide 8-1 mux (case statement)

sel din7 din6 din5 din4 din3 din2 din1 din0 dout
000 XX XX XX XX XX XX XX DD din0
001 XX XX XX XX XX XX DD XX din1
010 XX XX XX XX XX DD XX XX din2
011 XX XX XX XX DD XX XX XX din3
100 XX XX XX DD XX XX XX XX din4
101 XX XX DD XX XX XX XX XX din5
110 XX DD XX XX XX XX XX XX din6
111 DD XX XX XX XX XX XX XX din7

 

2  decoder 解码器/译码器

    n 个输入  =>  2n 个输出

1)  3-8 binary decoder

module  decoder3_8(A, Y);
  input    [2:0]  A;
  output  [7:0]  Y;
  reg    [7:0]  Y;

always @ (A)
  case (A)
    0:  Y = 8'b00000001;
    1:  Y = 8'b00000010;
    2:  Y = 8'b00000100;
    3:  Y = 8'b00001000;
    4:  Y = 8'b00010000;
    5:  Y = 8'b00100000;
    6:  Y = 8'b01000000;
    7:  Y = 8'b10000000;
    default:  Y = 8'b0;
  endcase

endmodule
decoder3_8

2)  3-6 binary decoder with enable

module  decoder3_6(A, EN, Y);
  input    EN;
  input    [2:0]  A;
  output  [5:0]  Y;
  reg    [5:0]  Y;

always @ (EN or A)
  case ({EN, A})
    4'b1000:  Y = 6'b000001;
    4'b1001:  Y = 6'b000010;
    4'b1010:  Y = 6'b000100;
    4'b1011:  Y = 6'b001000;
    4'b1100:  Y = 6'b010001;
    4'b1101:  Y = 6'b100000;
    default:  Y = 6'b0;
  endcase

endmodule
decoder3_6_en

 

你可能感兴趣的:(Verilog (二) multiplexer and decoder)