Error: (vsim-3053) D:/adder/adder_controltb.v(60): Illegal output or inout port connection (port 'P0

Error: (vsim-3053) D:/adder/adder_controltb.v(60): Illegal output or inout port connection (port 'P0_i').  

最终解决与下面几个链接虽然无关，但看了之后还是得到了启发。

http://www.edaboard.com/ftopic329717.html
http://xjhit.spaces.eepw.com.cn/articles/article/item/73905
双向总线的端口的写法等等。

标题：Verilog inout 双向口使用和仿真 转

2010-03-11 16:06:58

芯片外部引脚很多都使用inout类型的，为的是节省管腿。一般信号线用做总线等双向数据传输的时候就要用到INOUT类型了。就是一个端口同时做输入和输出。 inout在具体实现上一般用三态门来实现。三态门的第三个状态就是高阻'Z'。当inout端口不输出时，将三态门置高阻。这样信号就不会因为两端同时输出而出错了,更详细的内容可以搜索一下三态门tri-state的资料. 1 使用inout类型数据,可以用如下写法: inout data_inout; input data_in; reg data_reg;//data_inout的映象寄存器 reg link_data; assign data_inout=link_data?data_reg:1’bz;//link_data控制三态门 //对于data_reg,可以通过组合逻辑或者时序逻辑根据data_in对其赋值.通过控制link_data的高低电平,从而设置data_inout是输出数据还是处于高阻态,如果处于高阻态,则此时当作输入端口使用.link_data可以通过相关电路来控制. 2 编写测试模块时,对于inout类型的端口,需要定义成wire类型变量,而其它输入端口都定义成reg类型,这两者是有区别的. 当上面例子中的data_inout用作输入时,需要赋值给data_inout,其余情况可以断开.此时可以用assign语句实现:assign data_inout=link?data_in_t:1’bz;其中的link ,data_in_t是reg类型变量,在测试模块中赋值. 另外,可以设置一个输出端口观察data_inout用作输出的情况: Wire data_out_t; Assign data_out_t=(!link)?data_inout:1’bz;   3 else，in RTL inout use in top module(PAD) dont use inout(tri) in sub module 也就是说，在内部模块最好不要出现inout，如果确实需要，那么用两个port实现，到顶层的时候再用三态实现。理由是：在非顶层模块用双向口的话，该双向口必然有它的上层跟它相连。既然是双向口，则上层至少有一个输入口和一个输出口联到该双向口上，则发生两个内部输出单元连接到一起的情况出现，这样在综合时往往会出错。 对双向口，我们可以将其理解为2个分量：一个输入分量，一个输出分量。另外还需要一个控制信号控制输出分量何时输出。此时，我们就可以很容易地对双向端口建模。 例子： CODE: module dual_port ( .... inout_pin, .... ); inout inout_pin; wire inout_pin; wire input_of_inout; wire output_of_inout; wire out_en; assign input_of_inout = inout_pin; assign inout_pin = out_en ? output_of_inout : 高阻;//问题，如果out_en为假的话，inout_pin为高                                                    //阻，那input_of_inout呢？                                                    //如果out_en为真，那么input_of_inout岂不                                                    //是也等于inout_pin？怎么体现是输入呢？ endmodule 可见，此时input_of_inout和output_of_inout就可以当作普通信号使用了。   4.仿真（o(∩_∩)o...哈哈，这才是我想要看的） 在仿真的时候，需要注意双向口的处理。如果是直接与另外一个模块的双向口连接，那么只要保证一个模块在输出的时候，另外一个模块没有输出（处于高阻态）就可以了。 如果是在ModelSim中作为单独的模块仿真，那么在模块输出的时候，不能使用force命令将其设为高阻态，而是使用release命令将总线释放掉 很多初学者在写testbench进行仿真和验证的时候，被inout双向口难住了。仿真器老是提示错误不能进行。下面是我个人对inout端口写testbench仿真的一些总结，并举例进行说明。在这里先要说明一下inout口在testbench中要定义为wire型变量。 先假设有一源代码为： module xx(data_inout , ........); inout data_inout; ........................ assign data_inout=(! link)?datareg:1'bz; endmodule 方法一：使用相反控制信号inout口，等于两个模块之间用inout双向口互连。这种方法要注意assign 语句只能放在initial和always块内。 module test(); wire data_inout; reg data_reg; reg link; initial begin .......... end assign data_inout=link?data_reg:1'bz; endmodule 方法二：使用force和release语句，但这种方法不能准确反映双向端口的信号变化，但这种方法可以反在块内。 module test(); wire data_inout; reg data_reg; reg link; #xx;        //延时 force data_inout=1'bx;           //强制作为输入端口 ............... #xx; release data_inout;          //释放输入端口 endmodule   仿真 很多读者反映仿真双向端口的时候遇到困难，这里介绍一下双向端口的仿真方法。一个典型的双向端口如图1所示。 其中inner_port与芯片内部其他逻辑相连，outer_port为芯片外部管脚，out_en用于控制双向端口的方向，out_en为1时，端口为输出方向，out_en为0时，端口为输入方向。 用Verilog语言描述如下： module bidirection_io(inner_port,out_en,outer_port); input out_en; inout[7:0] inner_port; inout[7:0] outer_port; assign outer_port=(out_en==1)?inner_port:8'hzz; assign inner_port=(out_en==0)?outer_port:8'hzz; endmodule 用VHDL语言描述双向端口如下： library ieee; use IEEE.STD_LOGIC_1164.ALL; entity bidirection_io is port ( inner_port : inout std_logic_vector(7 downto 0); out_en : in std_logic; outer_port : inout std_logic_vector(7 downto 0) ); end bidirection_io; architecture behavioral of bidirection_io is begin outer_port<=inner_port when out_en='1' else (OTHERS=>'Z'); inner_port<=outer_port when out_en='0' else (OTHERS=>'Z'); end behavioral; 仿真时需要验证双向端口能正确输出数据，以及正确读入数据，因此需要驱动out_en端口，当out_en端口为1时，testbench驱动inner_port端口，然后检查outer_port端口输出的数据是否正确；当out_en端口为0时，testbench驱动outer_port端口，然后检查inner_port端口读入的数据是否正确。由于inner_port和outer_port端口都是双向端口（在VHDL和Verilog语言中都用inout定义），因此驱动方法与单向端口有所不同。 验证该双向端口的testbench结构如图2所示。 这是一个self-checking testbench，可以自动检查仿真结果是否正确，并在Modelsim控制台上打印出提示信息。图中Monitor完成信号采样、结果自动比较的功能。 testbench的工作过程为 1）out_en=1时，双向端口处于输出状态，testbench给inner_port_tb_reg信号赋值，然后读取outer_port_tb_wire的值，如果两者一致，双向端口工作正常。 2）out_en=0时，双向端口处于输如状态，testbench给outer_port_tb_reg信号赋值，然后读取inner_port_tb_wire的值，如果两者一致，双向端口工作正常。 用Verilog代码编写的testbench如下，其中使用了自动结果比较，随机化激励产生等技术。 `timescale 1ns/10ps module tb(); reg[7:0] inner_port_tb_reg; wire[7:0] inner_port_tb_wire; reg[7:0] outer_port_tb_reg; wire[7:0] outer_port_tb_wire; reg out_en_tb; integer i; initial begin out_en_tb=0; inner_port_tb_reg=0; outer_port_tb_reg=0; i=0; repeat(20) begin #50 i=$random; out_en_tb=i[0]; //randomize out_en_tb inner_port_tb_reg=$random; //randomize data outer_port_tb_reg=$random; end end //**** drive the ports connecting to bidirction_io assign inner_port_tb_wire=(out_en_tb==1)?inner_port_tb_reg:8'hzz; assign outer_port_tb_wire=(out_en_tb==0)?outer_port_tb_reg:8'hzz; //最不懂的就是这儿了，估计也是最重要的地儿 //instatiate the bidirction_io module bidirection_io bidirection_io_inst(.inner_port(inner_port_tb_wire), .out_en(out_en_tb), .outer_port(outer_port_tb_wire)); //***** monitor ****** always@(out_en_tb,inner_port_tb_wire,outer_port_tb_wire) begin #1; if(outer_port_tb_wire===inner_port_tb_wire) begin $display("\n **** time=%t ****",$time); $display("OK! out_en=%d",out_en_tb); $display("OK! outer_port_tb_wire=%d,inner_port_tb_wire=%d", outer_port_tb_wire,inner_port_tb_wire); end else begin $display("\n **** time=%t ****",$time); $display("ERROR! out_en=%d",out_en_tb); $display("ERROR! outer_port_tb_wire != inner_port_tb_wire" ); $display("ERROR! outer_port_tb_wire=%d, inner_port_tb_wire=%d", outer_port_tb_wire,inner_port_tb_wire); end end endmodule

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Thread: Inout Error When Designing A Counter Test Bench

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1. 04-10-08, 01:46 #1
   fjrrulz 

   

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   vsim 3015

   I am designing a 4-bit counter with enable, load, reset, input data, output Y, and an overflow flag RCA. Here is my code:
   
   

   Code:

   module counter(clk, data, Y, RCA, load, reset, enable);
      input clk;
      input [3:0]data;
      input load;
      input reset;
      input enable;
      output [3:0]Y = 4'b0000;
      output RCA = 0;
      
      reg [3:0]Y;
      reg RCA;
      
      wire reset = 1'b0;
      
      always @ (negedge clk)
         begin
         RCA = 0;
             if (reset == 1'b1)
                begin
                    if (Y[3:0] < 4'b1111)
                       begin
                    if (load == 1'b1)
                       Y[3:0] = data[3:0];
                    else if (enable == 1'b0)
                            Y[3:0] = Y[3:0] + 4'b0001;
                         else
                            Y[3:0] = Y[3:0];
                       end
                   else
                      RCA = 1'b1;
                      Y[3:0] = 4'b0000;
                end
             else
                Y[3:0] = 4'b0000;
       end
   endmodule

   Here is the test bench I wrote for the counter:
   
   

   Code:

   module counter_test;
       reg reset;
       reg clk;
       reg load;
       reg enable;
       reg [3:0]data;
       wire RCA;
       wire [3:0]Y;
           
       counter counter0(clk,Y,reset,enable,load,RCA,data);
          initial clk = 0;
          always
          #10 clk = ~clk;
          
       counter counter1(clk,Y,reset,enable,load,RCA,data);
          initial begin
              reset = 0;
              load = 1;
              enable = 1;
              data[3:0] = 4'b0110;
              #25;
              reset = 1;
              #20;
              load = 0;
              #40;
              enable = 0;
              #20;
              enable = 1;
          end
   endmodule

   The programs compile fine, but I am getting the following warnings and errors during simulation:
   
   

   Code:

   ** Error: (vsim-3053) C:/Users/Fred/Desktop/Homework/counter_test.v(10): Illegal output or inout port connection (port 'Y').
   #         Region: /counter_test/counter0
   # ** Warning: (vsim-3015) C:/Users/Fred/Desktop/Homework/counter_test.v(10): [PCDPC] - Port size (4 or 4) does not match connection size (1) for port 'Y'.
   #         Region: /counter_test/counter0
   # ** Error: (vsim-3053) C:/Users/Fred/Desktop/Homework/counter_test.v(10): Illegal output or inout port connection (port 'RCA').
   #         Region: /counter_test/counter0
   # ** Warning: (vsim-3015) C:/Users/Fred/Desktop/Homework/counter_test.v(10): [PCDPC] - Port size (1 or 1) does not match connection size (4) for port 'enable'.
   #         Region: /counter_test/counter0
   # ** Error: (vsim-3053) C:/Users/Fred/Desktop/Homework/counter_test.v(15): Illegal output or inout port connection (port 'Y').
   #         Region: /counter_test/counter1
   # ** Warning: (vsim-3015) C:/Users/Fred/Desktop/Homework/counter_test.v(15): [PCDPC] - Port size (4 or 4) does not match connection size (1) for port 'Y'.
   #         Region: /counter_test/counter1
   # ** Error: (vsim-3053) C:/Users/Fred/Desktop/Homework/counter_test.v(15): Illegal output or inout port connection (port 'RCA').
   #         Region: /counter_test/counter1
   # ** Warning: (vsim-3015) C:/Users/Fred/Desktop/Homework/counter_test.v(15): [PCDPC] - Port size (1 or 1) does not match connection size (4) for port 'enable'.
   #         Region: /counter_test/counter1

   Can anyone see my problem?
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2. 04-10-08, 14:27 #2
   j_andr 

   

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   error: (vsim-3053)

    Originally Posted by  fjrrulz

   /.../

   you have a different order of ports in module
   description and in instantiation;
   do not assume if the names are the same they
   will be connected correctly;
   either change the order or use:
   .clk(clk), .data(data), ...
   
   and it's not clear for me why you implement
   the counter twice;
   ---

   
   
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3. 04-10-08, 20:22 #3
   dcreddy1980 

   

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   ** error: (vsim-3053

   Change the counters instantiation in the testbench to :
   
   counter counter0(clk, data, Y0, RCA0, load, reset, enable);
   
   counter counter1(clk, data, Y1, RCA1, load, reset, enable);
   
   You have used the same o/p name for the two counters as Y and RCA which would give u a conflict , there is alos one more thing which u should take care, u have used ordered port mapping and the order of the port mapping is not the same as that of u r module declaration which is dangerous some times and thats the reason for those warnings.
   
   Plz declare YO,Y1 and RCA0,RCA1 and rerun the simulation and u should not see any warnings.

   
   
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4. 05-10-08, 02:24 #4
   fjrrulz 

   

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   counter with testbench

   Wow, it was the order of the ports. EXTREMELY stupid mistake. Thanks guys. 
   
   Added after 3 hours 7 minutes:
   
   OK, so the counter and test bench are posted above. I now have to combine 2 of these 4-bit counters to make an 8-bit counter. Does anyone know how to implement this? I know I have to connect the RCA flag of the first counter to the enable input of the second counter. But, how do I connect two modules together?