`timescale 1ns/1ns module AND2_TEST;//repeat(3)

/* fig1-9.tst */
`timescale 1ns/1ns
module AND2_TEST;
   reg A, B;
   wire OUT;
   AND2 AND2 (A, B, OUT);
   initial
   begin
   A = 0; B = 0;
   repeat(3)
   begin
   #100 A = 1;
   #100 A = 0; B = 1;
   #100 A = 1;
   #100 A=0;B=0;
   end
   #200 ;
   end
endmodule