Debug U-boot with BDI2000
今天终于把U-boot搞定了。
简单记录，以作备查。
1. 配置BDI2000 (参考BDI2000手册)
2. 写配置文件 (参考BDI2000手册, 以及DDR2和Marvell 88F6281手册)，初始化流程参考u-boot对DDR2的初始化代码。
3. 连接BDI2000与88F6281 target板，上电，然后通过网络telnet上BDI2000.
4. 下载u-boot到DDR中（BDI命令：LOAD），(注意，下载ELF文件到DDR 0x600000地址，此ELF文件不能被完全下载，但是可以成功执行)。
5. 运行下载至DDR中的u-boot(BDI命令：GO 0x670000)。(地址，从0x670000开始)
6. 此时通过串口能看见u-boot已经成功运行起来。然后通过bubt(Marvell专有命令)将u-boot烧写到NAND Flash中。
7. 断开BDI2000与板子的连接。u-boot即可成功运行。
贴出88F6281的BDI2000配置文件如下：
[INIT]
WREG CPSR 0x000000d3 ; set the cpu to SVC32 mode
WCP15 0x1 0x00052078 ; MMU disable,
WM32 0xD00100e0 0x1B1B9B9B ; IO configurion 0 register
WM32 0xD0001400 0x43000c30 ; SDRAM configurion register
WM32 0xD0001404 0x39543000 ; DDR controller control (low) register
WM32 0xD0001408 0x22125451 ; SDRAM timing (low) register
WM32 0xD000140C 0x00000833 ; SDRAM timing (high) register
WM32 0xD0001410 0x000000cc ; SDRAM address control register
WM32 0xD0001414 0x00000000 ; SDRAM opne pages control register
WM32 0xD0001418 0x00000000 ; SDRAM operation register
WM32 0xD000141C 0x00000c52 ; SDRAM Mode register
WM32 0xD0001420 0x00000004 ; extend DRAM mode register
WM32 0xD0001424 0x0000F17F ; DDR controller control (high) register
WM32 0xD0001428 0x00085520 ; DDR timing (low) register
WM32 0xD000147C 0x00008552 ; DDR timing (high) register
WM32 0xD0001504 0x0FFFFFF1 ; CPU CS window0 size register
WM32 0xD0001508 0x10000000 ; CPU CS window1 base address register
WM32 0xD000150C 0x0FFFFFF5 ; CPU CS window1 size register
WM32 0xD0001514 0x00000000 ; CPU CS window2 size register
WM32 0xD000151C 0x00000000 ; CPU CS window3 size register
WM32 0xD0001494 0x00120012 ; SDRAM ODT control (low) register
WM32 0xD0001498 0x00000000 ; SDRAM ODT control (high) register
WM32 0xD000149C 0x0000E40F ; DDR Controller ODT control register
WM32 0xD0001480 0x00000001 ; SDRAM initialization register
WM32 0xD0010418 0x000c0282 ; NAND read Parameters register
WM32 0xD001041c 0x00010305 ; NAND write Parameters register
WM32 0xD0010470 0x01c00541 ; NAND flash control register
WM32 0xD0020134 0x66666666 ; L2 RAM timing 0 register
WM32 0xD0020138 0x66666666 ; L2 RAM timing 1 register
WM32 0xD0010000 0x01111111
WM32 0xD0010008 0x00551111
[TARGET]
CPUTYPE FERO926 ;
CLOCK 3 ; JTAG clock (0=Adaptive, 1=8MHz, 2=4MHz,...)
ENDIAN LITTLE ; memory model (LITTLE | BIG), the 88F5181 use Little edian
TRST PUSHPULL ; OPENDRAIN
RESET HARD 500
VECTOR CATCH 0x1F ; catch unhandled exceptions
BDIMODE AGENT ; the BDI working mode (LOADONLY | AGENT)
STARTUP RESET ; after the board power up, then reset it
BREAKMODE SOFT 0xdfffdfff ;SOFT or HARD
WAKEUP 1000
[HOST]
IP 10.5.2.19 ; this the host ip where the tftp locate at
FILE F:/BDI_debug/u-boot ;which file will be download to DDR SDRAM
FORMAT ELF ; the format can be SREC, BIN, AOUT, ELF, COFF, ROM
LOAD MANUAL ; <AGENT> load application MANUAL or AUTO after reset
START 0x600000 ; only the BIN file need to allocate the start address of the DDR SDRAM
PROMPT [BDI2000] ; this entry defines a new telnet prompt
;this is optional for this configuration file, if you want to operate the flash, this is needed, but it only can operate NOR
;flash
;[FLASH]
;CHIPTYPE STRATAX8 ; flash type: this parameter defines the type of flash used
;CHIPSIZE 0x1000000 ; the size of one flash chip in bytes
;BUSWIDTH 8 ; the width of the flash memory bus in bits (8 | 16 | 32), the 88F5181 use 16 MB 8-bit width
;NOR flash.
[REGS]
FILE $regFero926.def