Xilinx ISE:关于related logic和unrelated logic的问题

ISE综合布线生成的最终报告(Design Summary)或者MAP Report中：
Logic Distribution:
  Number of occupied Slices:        1,341 out of   9,280   14%
  Number of Slices containing only related logic:   1,341 out of   1,341  100%
  Number of Slices containing unrelated logic:          0 out of   1,341    0%
        *See NOTES below for an explanation of the effects of unrelated logic

两种logic（related logic和unrelated logic）的区别和联系?
http://www.edacn.net/bbs/viewthread.php?tid=13808
by 丁丁:
看 Xilinx的Slice内部结构图，一般是1个LUT和1个DFF构成1个LC，这种结构符合FPGA设计的一般规律，也就是作一些组合逻辑然后触发器 打一拍。但是不是所有的设计都是这样的，可能是几个LUT后才会打一拍，所以为了提高器件资源的利用率，Xilinx在LUT和DFF之间设计了抽头，允 许独自分别使用LUT或DFF，也就是两个不相关的逻辑可以放在同一个SLICE中，分别占用SLICE的LUT和DFF资源。当然这样做的前提是器件内 部的SLICE资源已经完全占用。所以在报告中，所谓realted logic就是一个SLICE中只有相关逻辑；而unrelated logic就是一个SLICE中放入了两部分无关逻辑。当SLICE占用率到了99％之后，就有可能出现unrelated logic了，否则100％都是related logic。所以说在看器件占用率的时候，不要只看Slice的占用率，要看LUT和DFF的占用率，即使SLICE占用率达到了99%，还是可以放入很 多逻辑的，这时unrelated logic的比例会增加，对于Xilinx的VII、VII Pro器件来说，布线资源很丰富，所以即使占用资源很多也还是可以跑通的。这也是相比Altera的一个优势吧，我见过的设计unrelated logic已经占用到50%了，还跑到83MHz，可以说是把器件用得很充分了。

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.