Nexys3开发板Verilog Demo

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 Nexys3开发板Verilog Demo

 

    这个学期开始学FPGA开发，使用的开发板是Nexys3，硬件编程语言是Verilog。苦于之前一直没有找到很好的代码学习资料，于是在这里将自己写过的一些相对简单的代码整理了一下分享开来，希望能对各位初学者有所帮助。

 

    本文提供的Verilog代码都是属于Demo级别的，不过限于本人水平，也不免会有一些瑕疵，这里仅供参考，还请各位慎思！(“博学、审问、慎思、明辨、笃行。” 我的校训啊！)

 

    如果各位还想学习更加复杂的Verilog project，请持续关注我以后的博客更新。(透个口风，我目前正在做的project有两个，微秒级秒表以及VGA显示。)

 

    注意：由于本文大部分Demo都是十分简单经典的Verilog模块，所以把题意部分也省了，直接上电路图和代码，如果发现代码有看不懂，可以下载文章末尾的附件，里面有更加详细的介绍。

 

 

目录

2输入逻辑门

2位比较器

4位2选一多路选择器

7段译码器

3-8译码器

8-3优先编码器

4位二进制-BCD 码转换器

4位RCA加法器

4位CLA加法器

4位移位器

4位移位寄存器

4位移位寄存器生成伪随机数列

7段译码器扫描显示2位

Traffic controller(Moore FSM)

Traffic controller(Mealy FSM)

 

 

1、2输入逻辑门

    简单的与门、与非门、或门、或非门、异或门、异或非门的实现。

2输入逻辑门电路图

 

// 设计文件: gate2.v
`timescale 1ns / 1ps

module gates2(input wire a, b,
				  output wire [5:0] y);
   assign y[0] = a & b;    // AND
   assign y[1] = ~(a & b); // NAND
   assign y[2] = a | b;    // OR
   assign y[3] = ~(a | b); // NOR
   assign y[4] = a ^ b;    // XOR
	assign y[5] = ~(a ^ b); // NXOR
endmodule

 

// 测试文件: gate2_test.v
`timescale 1ns / 1ps

module gates2_test;

	// Inputs
	reg a, b;
	// Outputs
	wire [5:0] y;

	// Instantiate the Unit Under Test (UUT)
	gates2 uut (
		.a(a),
		.b(b),
		.y(y)
	);

	initial begin
		// Initialize Inputs
		a = 0;
		b = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		#200
		a <= 0;
		b <= 0;
		#200
		a <= 0;
		b <= 1;
		#200
		a <= 1;
		b <= 0;
		#200
		a <= 1;
		b <= 1;
	end
      
endmodule

 

// 引脚文件：gate2_ucf.ucf
NET "a" LOC = "T5";
NET "b" LOC = "V8";
NET "y[0]" LOC = "U15";
NET "y[1]" LOC = "V15";
NET "y[2]" LOC = "M11";
NET "y[3]" LOC = "N11";
NET "y[4]" LOC = "R11";
NET "y[5]" LOC = "T11";

 

 

2、2位比较器

2位比较器真值表

 

// 设计文件：comp2bit.v
`timescale 1ns / 1ps

module comp2bit(
    input [1:0] a,
    input [1:0] b,
    output a_eq_b,
    output a_gt_b,
    output a_lt_b
    );

	assign a_eq_b = (a == b);
	assign a_gt_b = (a > b);
	assign a_lt_b = (a < b);

endmodule

 

// 测试文件：comp2bit_test.v
`timescale 1ns / 1ps

module comp2bit_test;

	// Inputs
	reg [1:0] a;
	reg [1:0] b;

	// Outputs
	wire a_eq_b;
	wire a_gt_b;
	wire a_lt_b;

	// Instantiate the Unit Under Test (UUT)
	comp2bit uut (
		.a(a), 
		.b(b), 
		.a_eq_b(a_eq_b), 
		.a_gt_b(a_gt_b), 
		.a_lt_b(a_lt_b)
	);

	initial begin
		// Initialize Inputs
		a = 0;
		b = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		a = 1;
		b = 0;
		#100;
		a = 2;
		b = 0;
		#100;
		a = 3;
		b = 0;
		#100;
		a = 0;
		b = 1;
		#100;
		a = 1;
		b = 1;
		#100;
		a = 2;
		b = 1;
		#100;
		a = 3;
		b = 1;
		#100;
		a = 0;
		b = 2;
		#100;
		a = 1;
		b = 2;
		#100;
		a = 2;
		b = 2;
		#100;
		a = 3;
		b = 2;
		#100;
		a = 0;
		b = 3;
		#100;
		a = 1;
		b = 3;
		#100;
		a = 2;
		b = 3;
		#100;
		a = 3;
		b = 3;
		#100;
	end
      
endmodule

 

// 引脚文件：comp2bit_ucf.ucf
NET "a[1]" LOC="T5";
NET "a[0]" LOC="V8";

NET "b[1]" LOC="U8";
NET "b[0]" LOC="N8";

NET "a_eq_b" LOC="T11";
NET "a_gt_b" LOC="R11";
NET "a_lt_b" LOC="N11";

 

 

3、4位2选一多路选择器

4位2选一多路选择器原理图

 

// 设计文件：mux24a.v
`timescale 1ns / 1ps

module mux24a(
    output [3:0] y,
    input [3:0] a,
    input [3:0] b,
    input s
    );

	assign y = (s == 0) ? a : b;

endmodule

 

// 测试文件：mux24a_test.v
`timescale 1ns / 1ps

module mux24a_test;

	// Inputs
	reg [3:0] a;
	reg [3:0] b;
	reg s;

	// Outputs
	wire [3:0] y;

	// Instantiate the Unit Under Test (UUT)
	mux24a uut (
		.y(y), 
		.a(a), 
		.b(b), 
		.s(s)
	);

	initial begin
		// Initialize Inputs
		a = 0;
		b = 0;
		s = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		a = 4'b0101;
		b = 4'b1010;
		#200;
		s = 1;
		#200;
		s = 0;
		#200;
		s = 1;
		#200;
		a = 4'b1001;
		b = 4'b0100;
		#200;
		s = 0;
		#200;
		s = 1;
	end
      
endmodule

 

// 引脚文件：mux24a_ucf.ucf
NET "a[3]" LOC="T5";
NET "a[2]" LOC="V8";
NET "a[1]" LOC="U8";
NET "a[0]" LOC="N8";

NET "b[3]" LOC="M8";
NET "b[2]" LOC="V9";
NET "b[1]" LOC="T9";
NET "b[0]" LOC="T10";

NET "y[3]" LOC="T11";
NET "y[2]" LOC="R11";
NET "y[1]" LOC="N11";
NET "y[0]" LOC="M11";

NET "s" LOC="C9";

 

 

4、7段译码器

7段译码器原理图

 

// 设计文件：hex7seg.v
`timescale 1ns / 1ps

module hex7seg(
    input [3:0] x,
	 output [3:0] an,
    output [6:0] seg
    );

	reg [6:0] seg;
	
	assign an = 4'b0000;
	always @ (x)
		case (x)
			4'b0000: seg <= 7'b0000001;
			4'b0001: seg <= 7'b1001111;
			4'b0010: seg <= 7'b0010010;
			4'b0011: seg <= 7'b0000110;
			4'b0100: seg <= 7'b1001100;
			4'b0101: seg <= 7'b0100100;
			4'b0110: seg <= 7'b0100000;
			4'b0111: seg <= 7'b0001111;
			4'b1000: seg <= 7'b0000000;
			4'b1001: seg <= 7'b0000100;
			4'b1010: seg <= 7'b0001000;
			4'b1011: seg <= 7'b1100000;
			4'b1100: seg <= 7'b0110001;
			4'b1101: seg <= 7'b1000010;
			4'b1110: seg <= 7'b0110000;
			4'b1111: seg <= 7'b0111000;
		endcase

endmodule

 

// 测试文件：hex7seg_test.v
`timescale 1ns / 1ps

module hex7seg_test;

	// Inputs
	reg [3:0] x;

	// Outputs
	wire [3:0] an;
	wire [6:0] seg;

	// Instantiate the Unit Under Test (UUT)
	hex7seg uut (
		.x(x), 
		.an(an), 
		.seg(seg)
	);

	initial begin
		// Initialize Inputs
		x = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		x = 0;
		#100;
		x = 1;
		#100;
		x = 2;
		#100;
		x = 3;
		#100;
		x = 4;
		#100;
		x = 5;
		#100;
		x = 6;
		#100;
		x = 7;
		#100;
		x = 8;
		#100;
		x = 9;
		#100;
		x = 10;
		#100;
		x = 11;
		#100;
		x = 12;
		#100;
		x = 13;
		#100;
		x = 14;
		#100;
		x = 15;
		#100;
	end
      
endmodule

 

// 引脚文件：hex7seg_ucf.ucf
NET "x[3]" LOC = "T5";
NET "x[2]" LOC = "V8";
NET "x[1]" LOC = "U8";
NET "x[0]" LOC = "N8";

NET "an[3]" LOC = "P17";
NET "an[2]" LOC = "P18";
NET "an[1]" LOC = "N15";
NET "an[0]" LOC = "N16";

NET "seg[6]" LOC = "T17";
NET "seg[5]" LOC = "T18";
NET "seg[4]" LOC = "U17";
NET "seg[3]" LOC = "U18";
NET "seg[2]" LOC = "M14";
NET "seg[1]" LOC = "N14";
NET "seg[0]" LOC = "L14";

 

 

5、3-8译码器

3-8译码器真值表

 

// 设计文件：decode38a.v
`timescale 1ns / 1ps

module decode38a(
    input [2:0] a,
    output [7:0] y
    );

	reg [7:0] y;
	
	always @ (a)
		case (a)
			3'b000: y <= 8'b0000_0001;
			3'b001: y <= 8'b0000_0010;
			3'b010: y <= 8'b0000_0100;
			3'b011: y <= 8'b0000_1000;
			3'b100: y <= 8'b0001_0000;
			3'b101: y <= 8'b0010_0000;
			3'b110: y <= 8'b0100_0000;
			3'b111: y <= 8'b1000_0000;
		endcase

endmodule

 

// 测试文件：decode38a_test.v
`timescale 1ns / 1ps

module decode38a_test;

	// Inputs
	reg [2:0] a;

	// Outputs
	wire [7:0] y;

	// Instantiate the Unit Under Test (UUT)
	decode38a uut (
		.a(a), 
		.y(y)
	);

	initial begin
		// Initialize Inputs
		a = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		a = 3'b000;
		#100;
		a = 3'b001;
		#100;
		a = 3'b010;
		#100;
		a = 3'b011;
		#100;
		a = 3'b100;
		#100;
		a = 3'b101;
		#100;
		a = 3'b110;
		#100;
		a = 3'b111;
		#100;
	end
      
endmodule

 

// 引脚文件：decode38a_ucf.ucf
NET "a[2]" LOC = "T5";
NET "a[1]" LOC = "V8";
NET "a[0]" LOC = "U8";

NET "y[7]" LOC = "T11";
NET "y[6]" LOC = "R11";
NET "y[5]" LOC = "N11";
NET "y[4]" LOC = "M11";
NET "y[3]" LOC = "V15";
NET "y[2]" LOC = "U15";
NET "y[1]" LOC = "V16";
NET "y[0]" LOC = "U16";

 

 

6、8-3优先编码器

8-3优先编码器真值表

 

// 设计文件：pencode83.v
`timescale 1ns / 1ps

module pencode83(
    input [7:0] x,
    output reg [2:0] y,
    output reg valid
    );
	always @ (x) begin
		if (x[7] == 1)
			y <= 3'b111;
		else if (x[6] == 1)
			y <= 3'b110;
		else if (x[5] == 1)
			y <= 3'b101;
		else if (x[4] == 1)
			y <= 3'b100;
		else if (x[3] == 1)
			y <= 3'b011;
		else if (x[2] == 1)
			y <= 3'b010;
		else if (x[1] == 1)
			y <= 3'b001;
		else if (x[0] == 1)
			y <= 3'b000;
		
		if (x == 8'b0000_0000)
			valid <= 0;
		else
			valid <= 1;
	end

endmodule

 

// 测试文件：pencode83_test.v
`timescale 1ns / 1ps

module pencode83_test;

	// Inputs
	reg [7:0] x;

	// Outputs
	wire [2:0] y;
	wire valid;

	// Instantiate the Unit Under Test (UUT)
	pencode83 uut (
		.x(x), 
		.y(y), 
		.valid(valid)
	);

	initial begin
		// Initialize Inputs
		x = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		x = 8'b0000_0000;
		#100;
		x = 8'b0000_0001;
		#100;
		x = 8'b0000_0011;
		#100;
		x = 8'b0000_0111;
		#100;
		x = 8'b0000_1111;
		#100;
		x = 8'b0001_1111;
		#100;
		x = 8'b0011_1111;
		#100;
		x = 8'b0111_1111;
		#100;
		x = 8'b1111_1111;
		#100;
	end
      
endmodule

 

// 引脚文件：pencode83_ucf.ucf
NET "x[7]" LOC = "T5";
NET "x[6]" LOC = "V8";
NET "x[5]" LOC = "U8";
NET "x[4]" LOC = "N8";
NET "x[3]" LOC = "M8";
NET "x[2]" LOC = "V9";
NET "x[1]" LOC = "T9";
NET "x[0]" LOC = "T10";

NET "y[2]" LOC = "T11";
NET "y[1]" LOC = "R11";
NET "y[0]" LOC = "N11";

NET "valid" LOC = "U16";

 

 

7、4位二进制-BCD 码转换器

4位二进制-BCD码转换器真值表

 

// 设计文件：binbcd4.v
`timescale 1ns / 1ps

module binbcd4(
    input [3:0] b,
    output reg [4:0] p
    );

	always @ (b) begin
		if (b <= 9)
			p <= {1'b0, b[3:0]};
		else
			p <= {1'b1, b[3:0]-4'b1010};
	end

endmodule

 

// 测试文件：binbcd4_test.v
`timescale 1ns / 1ps

module binbcd4_test;

	// Inputs
	reg [3:0] b;

	// Outputs
	wire [4:0] p;

	// Instantiate the Unit Under Test (UUT)
	binbcd4 uut (
		.b(b), 
		.p(p)
	);

	initial begin
		// Initialize Inputs
		b = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		b = 4'b0000;
		#100;
		b = 4'b0001;
		#100;
		b = 4'b0010;
		#100;
		b = 4'b0011;
		#100;
		b = 4'b0100;
		#100;
		b = 4'b0101;
		#100;
		b = 4'b0110;
		#100;
		b = 4'b0111;
		#100;
		b = 4'b1000;
		#100;
		b = 4'b1001;
		#100;
		b = 4'b1010;
		#100;
		b = 4'b1011;
		#100;
		b = 4'b1100;
		#100;
		b = 4'b1101;
		#100;
		b = 4'b1110;
		#100;
		b = 4'b1111;
		#100;
	end
      
endmodule

 

// 引脚文件：binbcd4_ucf.ucf
NET "b[3]" LOC = "T5";
NET "b[2]" LOC = "V8";
NET "b[1]" LOC = "U8";
NET "b[0]" LOC = "N8";

NET "p[4]" LOC = "T11";
NET "p[3]" LOC = "R11";
NET "p[2]" LOC = "N11";
NET "p[1]" LOC = "M11";
NET "p[0]" LOC = "V15";

 

 

 

8、4位RCA加法器

4位RCA加法器

 

 

// 设计文件：adder4a.v
`timescale 1ns / 1ps

module FA(
    input a, b, cin,
	 output cout, sum
	 );
	 assign sum = a ^ b ^ cin;
	 assign cout = a & b | a & cin | b & cin;
endmodule

module adder4a(
    input [3:0] a,
    input [3:0] b,
    output [3:0] s,
    output cf,
    output ovf
    );
	wire c0, c1, c2;
	
	FA fa0(a[0], b[0], 1'b0, c0, s[0]);
	FA fa1(a[1], b[1], c0, c1, s[1]);
	FA fa2(a[2], b[2], c1, c2, s[2]);
	FA fa3(a[3], b[3], c2, cf, s[3]);
	assign ovf = c2 ^ cf;
endmodule

 

// 测试文件：adder4a_test.v
`timescale 1ns / 1ps

module adder4a_test;

	// Inputs
	reg [3:0] a;
	reg [3:0] b;

	// Outputs
	wire [3:0] s;
	wire cf;

	// Instantiate the Unit Under Test (UUT)
	adder4a uut (
		.a(a), 
		.b(b), 
		.s(s), 
		.cf(cf),
		.ovf(ovf)
	);

	initial begin
		// Initialize Inputs
		a = 0;
		b = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		a = 4'b0000;
		b = 4'b0001;
		#100;
		a = 4'b0000;
		b = 4'b0010;
		#100;
		a = 4'b0000;
		b = 4'b0011;
		#100;
		a = 4'b0111;
		b = 4'b0000;
		#100;
		a = 4'b0111;
		b = 4'b0001;
		#100;
		a = 4'b0111;
		b = 4'b0010;
		#100;
		a = 4'b0111;
		b = 4'b0011;
		#100;
		a = 4'b1111;
		b = 4'b0000;
		#100;
		a = 4'b1111;
		b = 4'b0001;
		#100;
		a = 4'b1111;
		b = 4'b0010;
		#100;
		a = 4'b1111;
		b = 4'b0011;
		#100;
	end
      
endmodule

 

// 引脚文件：adder4a_ucf.ucf
NET "a[3]" LOC = "T5";
NET "a[2]" LOC = "V8";
NET "a[1]" LOC = "U8";
NET "a[0]" LOC = "N8";

NET "b[3]" LOC = "M8";
NET "b[2]" LOC = "V9";
NET "b[1]" LOC = "T9";
NET "b[0]" LOC = "T10";

NET "s[3]" LOC = "T11";
NET "s[2]" LOC = "R11";
NET "s[1]" LOC = "N11";
NET "s[0]" LOC = "M11";

NET "cf" LOC = "V16";
NET "ovf" LOC = "U16";

 

 

 

9、4位CLA加法器

4位CLA加法器框图

 

// 设计文件：adder4a_cla.v
`timescale 1ns / 1ps

module adder4a_cla(
    input [3:0] a,
    input [3:0] b,
    output [3:0] s,
    output cf,
    output ovf
    );
	wire G[3:0], P[3:0];
	wire c0, c1, c2;
	
	assign G[0] = a[0] & b[0];
	assign G[1] = a[1] & b[1];
	assign G[2] = a[2] & b[2];
	assign G[3] = a[3] & b[3];
	
	assign P[0] = a[0] | b[0];
	assign P[1] = a[1] | b[1];
	assign P[2] = a[2] | b[2];
	assign P[3] = a[3] | b[3];
	
	assign c0 = G[0] | P[0] & 1'b0;
	assign c1 = G[1] | G[0] & P[1] | P[0] & P[1] & 1'b0;
	assign c2 = G[2] | G[1] & P[2] | G[0] & P[1] & P[2] | P[0]& P[1] & P[2] & 1'b0;
	assign cf = G[3] | G[2] & P[3] | G[1] & P[2] & P[3] | G[0] & P[1] & P[2] & P[3] | P[0] & P[1] & P[2] & P[3] & 1'b0;
	
	assign ovf = c2 ^ cf;
	assign s[0] = a[0] ^ b[0];
	assign s[1] = a[1] ^ b[1] ^ c0;
	assign s[2] = a[2] ^ b[2] ^ c1;
	assign s[3] = a[3] ^ b[3] ^ c2;
endmodule

 

// 测试文件：adder4a_cla_test.v
`timescale 1ns / 1ps

module adder4a_cla_test;

	// Inputs
	reg [3:0] a;
	reg [3:0] b;

	// Outputs
	wire [3:0] s;
	wire cf;
	wire ovf;

	// Instantiate the Unit Under Test (UUT)
	adder4a_cla uut (
		.a(a), 
		.b(b), 
		.s(s), 
		.cf(cf), 
		.ovf(ovf)
	);

	initial begin
		// Initialize Inputs
		a = 0;
		b = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		a = 4'b0000;
		b = 4'b0001;
		#100;
		a = 4'b0000;
		b = 4'b0010;
		#100;
		a = 4'b0000;
		b = 4'b0011;
		#100;
		a = 4'b0111;
		b = 4'b0000;
		#100;
		a = 4'b0111;
		b = 4'b0001;
		#100;
		a = 4'b0111;
		b = 4'b0010;
		#100;
		a = 4'b0111;
		b = 4'b0011;
		#100;
		a = 4'b1111;
		b = 4'b0000;
		#100;
		a = 4'b1111;
		b = 4'b0001;
		#100;
		a = 4'b1111;
		b = 4'b0010;
		#100;
		a = 4'b1111;
		b = 4'b0011;
		#100;
	end
      
endmodule

 

// 引脚文件：adder4a_cla_ucf.ucf
NET "a[3]" LOC = "T5";
NET "a[2]" LOC = "V8";
NET "a[1]" LOC = "U8";
NET "a[0]" LOC = "N8";

NET "b[3]" LOC = "M8";
NET "b[2]" LOC = "V9";
NET "b[1]" LOC = "T9";
NET "b[0]" LOC = "T10";

NET "s[3]" LOC = "T11";
NET "s[2]" LOC = "R11";
NET "s[1]" LOC = "N11";
NET "s[0]" LOC = "M11";

NET "cf" LOC = "V16";
NET "ovf" LOC = "U16";

 

 

 

10、4位移位器

4位移位器框图和功能表

 

 

// 设计文件：shift4.v
`timescale 1ns / 1ps

module shift4(
    input [2:0] s,
    input [3:0] d,
    output reg [3:0] y
    );
	always @ (s or d) begin
		case (s)
			3'b000: y <= d;
			3'b001: y <= {1'b0, d[3:1]};
			3'b010: y <= {d[2:0], 1'b0};
			3'b011: y <= {d[0], d[3:1]};
			3'b100: y <= {d[2:0], d[3]};
			3'b101: y <= {d[3], d[3:1]};
			3'b110: y <= {d[1], d[0], d[3:2]};
			3'b111: y <= d;
		endcase
	end
endmodule

 

// 测试文件：shift4_test.v
`timescale 1ns / 1ps

module shift4_test;

	// Inputs
	reg [2:0] s;
	reg [3:0] d;

	// Outputs
	wire [3:0] y;

	// Instantiate the Unit Under Test (UUT)
	shift4 uut (
		.s(s), 
		.d(d), 
		.y(y)
	);

	initial begin
		// Initialize Inputs
		s = 0;
		d = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		d = 4'b0010;
		#100;
		s = 3'b000;
		#100;
		s = 3'b001;
		#100;
		s = 3'b010;
		#100;
		s = 3'b011;
		#100;
		s = 3'b100;
		#100;
		s = 3'b101;
		#100;
		s = 3'b110;
		#100;
		s = 3'b111;
		#100;
	end
      
endmodule

 

// 引脚文件：shift4_ucf.ucf
NET "s[2]" LOC = "T5";
NET "s[1]" LOC = "V8";
NET "s[0]" LOC = "U8";

NET "d[3]" LOC = "M8";
NET "d[2]" LOC = "V9";
NET "d[1]" LOC = "T9";
NET "d[0]" LOC = "T10";

NET "y[3]" LOC = "T11";
NET "y[2]" LOC = "R11";
NET "y[1]" LOC = "N11";
NET "y[0]" LOC = "M11";

 

 

 

11、4位移位寄存器

4位移位寄存器电路图

 

 

// 设计文件：shiftreg.v
`timescale 1ns / 1ps

module shiftreg(
    input data_in,
    input clk,
    input clr,
    output reg [3:0] q
    );
	always @ (posedge clr or posedge clk)
	begin
		if (clr == 1)
			q <= 4'b0000;
		else
			q <= {data_in, q[3:1]};
	end
endmodule

 

// 测试文件：shiftreg_test.v
`timescale 1ns / 1ps

module shiftreg_test;

	// Inputs
	reg data_in;
	reg clk;
	reg clr;

	// Outputs
	wire [3:0] q;

	// Instantiate the Unit Under Test (UUT)
	shiftreg uut (
		.data_in(data_in), 
		.clk(clk), 
		.clr(clr), 
		.q(q)
	);

	initial begin
		// Initialize Inputs
		data_in = 0;
		clk = 0;
		clr = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		#100;
		clr = 1; data_in = 1;
		#100;
		clk = 1;
		#100;
		clk = 0; clr = 0;
		#100;
		clk = 1;
		#100;
		clk = 0;
		#100;
		clk = 1;
		#100;
		clk = 0;
		#100;
		clk = 1;
		#100;
		clk = 0;
		#100;
		clk = 1;
		#100;
		clk = 0; clr = 1;
	end
endmodule

 

// 引脚文件：shiftreg_ucf.ucf
NET "data_in" LOC = "T5";
NET "clk" LOC = "C9";
NET "clr" LOC = "B8";

NET "q[3]" LOC = "T11";
NET "q[2]" LOC = "R11";
NET "q[1]" LOC = "N11";
NET "q[0]" LOC = "M11";

 

 

 

12、4位移位寄存器生成伪随机数列

// 设计文件：pseurandseq.v
`timescale 1ns / 1ps

module pseurandseq(
    input clk,
    input clr,
    output reg [7:0] q
    );
	always @ (posedge clr or posedge clk)
	begin
		if (clr == 1)
			q <= 4'b00001000;
		else
			q <= {q[3:0], q[0], q[3:2], q[0]^q[1]};
	end
endmodule

 

// 测试文件：pseurandseq_test.v
`timescale 1ns / 1ps

module pseurandseq_test;

	// Inputs
	reg clk;
	reg clr;

	// Outputs
	wire [7:0] q;
	
	integer i;

	// Instantiate the Unit Under Test (UUT)
	pseurandseq uut (
		.clk(clk), 
		.clr(clr), 
		.q(q)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		clr = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		clr = 1;
		#100;
		clr = 0;
		#100;
		
		for (i=0; i<32; i=i+1)
		begin
			clk = 1;
			#100;
			clk = 0;
			#100;
		end
	end
      
endmodule

 

// 引脚文件：pseurandseq_ucf.ucf
NET "clk" LOC = "C9";
NET "clr" LOC = "B8";

NET "q[7]" LOC = "T11";
NET "q[6]" LOC = "R11";
NET "q[5]" LOC = "N11";
NET "q[4]" LOC = "M11";
NET "q[3]" LOC = "V15";
NET "q[2]" LOC = "U15";
NET "q[1]" LOC = "V16";
NET "q[0]" LOC = "U16";

 

 

13、7段译码器扫描显示2位

 

// 设计文件：Hex7seg2num.v
`timescale 1ns / 1ps

module Hex7seg2num(
    input clk,
    input clr,
    input [3:0] high,
    input [3:0] low,
    output reg [3:0] an,
    output reg [6:0] seg
    );
	parameter CLK_COUNT = 249999;
	reg [31:0] count;
	reg mclk;
	
	always @ (posedge clk)
	begin
		if (clr)
		begin
			count <= 0;
			mclk <= 0;
		end
		else if (count == CLK_COUNT)
		begin
			count <= 0;
			mclk <= ~mclk;
		end
		else
			count <= count+1;
	end
	
	always @ (mclk)
	begin
		if (mclk == 0)
		begin
			an <= 4'b1101;
			case(high)
				4'b0000: seg <= 7'b0000001;
				4'b0001: seg <= 7'b1001111;
				4'b0010: seg <= 7'b0010010;
				4'b0011: seg <= 7'b0000110;
				4'b0100: seg <= 7'b1001100;
				4'b0101: seg <= 7'b0100100;
				4'b0110: seg <= 7'b0100000;
				4'b0111: seg <= 7'b0001111;
				4'b1000: seg <= 7'b0000000;
				4'b1001: seg <= 7'b0000100;
				4'b1010: seg <= 7'b0001000;
				4'b1011: seg <= 7'b1100000;
				4'b1100: seg <= 7'b0110001;
				4'b1101: seg <= 7'b1000010;
				4'b1110: seg <= 7'b0110000;
				4'b1111: seg <= 7'b0111000;
			endcase
		end
		else if (mclk == 1)
		begin
			an <= 4'b1110;
			case(low)
				4'b0000: seg <= 7'b0000001;
				4'b0001: seg <= 7'b1001111;
				4'b0010: seg <= 7'b0010010;
				4'b0011: seg <= 7'b0000110;
				4'b0100: seg <= 7'b1001100;
				4'b0101: seg <= 7'b0100100;
				4'b0110: seg <= 7'b0100000;
				4'b0111: seg <= 7'b0001111;
				4'b1000: seg <= 7'b0000000;
				4'b1001: seg <= 7'b0000100;
				4'b1010: seg <= 7'b0001000;
				4'b1011: seg <= 7'b1100000;
				4'b1100: seg <= 7'b0110001;
				4'b1101: seg <= 7'b1000010;
				4'b1110: seg <= 7'b0110000;
				4'b1111: seg <= 7'b0111000;
			endcase
		end
	end
endmodule

 

// 测试文件：Hex7seg2num_test.v
`timescale 1ns / 1ps

module Hex7seg2num_test;

	// Inputs
	reg clk;
	reg clr;
	reg [3:0] high;
   reg [3:0] low;
    

	// Outputs
	wire [3:0] an;
   wire [6:0] seg;

	// Instantiate the Unit Under Test (UUT)
	Hex7seg2num uut (
		.clk(clk), 
		.clr(clr), 
		.high(high),
      .low(low),
		.an(an),
		.seg(seg)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		clr = 0;
		high = 0;
		low = 0;

		// Wait 5 ns for global reset to finish
		#5;
        
		// Add stimulus here
		clr = 1;
		high = 2;
		low = 4;
		#5;
		clr = 0;
	end
   
	always #5
		clk = ~clk;
endmodule

 

// 引脚文件：Hex7seg2num_ucf.ucf
NET "clk" LOC = "V10";
NET "clr" LOC = "C9";

NET "high[3]" LOC = "T5";
NET "high[2]" LOC = "V8";
NET "high[1]" LOC = "U8";
NET "high[0]" LOC = "N8";

NET "low[3]" LOC = "M8";
NET "low[2]" LOC = "V9";
NET "low[1]" LOC = "T9";
NET "low[0]" LOC = "T10";

NET "an[3]" LOC = "P17";
NET "an[2]" LOC = "P18";
NET "an[1]" LOC = "N15";
NET "an[0]" LOC = "N16";

NET "seg[6]" LOC = "T17";
NET "seg[5]" LOC = "T18";
NET "seg[4]" LOC = "U17";
NET "seg[3]" LOC = "U18";
NET "seg[2]" LOC = "M14";
NET "seg[1]" LOC = "N14";
NET "seg[0]" LOC = "L14";

 

 

14、Traffic controller(Moore FSM)

Moore FSM状态转换图

 

 

// 设计文件：trafficcontrollermoore.v
`timescale 1ns / 1ps

module trafficcontrollermoore(
    input TA,
    input TB,
    input clk,
    input clr,
    output reg [2:0] LA,
    output reg [2:0] LB
    );

	reg [1:0] state, nextstate;
	reg [31:0] count;
	reg mclk;
	
	parameter S0 = 2'b00;
	parameter S1 = 2'b01;
	parameter S2 = 2'b10;
	parameter S3 = 2'b11;
	
	parameter GREEN = 3'b100;
	parameter YELLOW = 3'b010;
	parameter RED = 3'b001;
	
	parameter CLK_COUNT = 4; //板级验证的时候该值改为249999999;
	
	always @ (posedge clk or posedge clr)
	begin
		if (clr)
		begin
			count <= 0;
			mclk <= 0;
		end
		else if (count == CLK_COUNT)
		begin
			count <= 0;
			mclk <= ~mclk;
		end
		else
			count <= count+1;
	end
	
	always @ (posedge mclk or posedge clr)
	begin
		if (clr)
			state <= S0;
		else
			state <= nextstate;
	end
	
	always @ (*)
	begin
		case (state)
			S0: if (TA) nextstate = S0;
					else nextstate = S1;
			S1: nextstate = S2;
			S2: if (TB) nextstate = S2;
					else nextstate = S3;
			S3: nextstate = S0;
			default: nextstate = S0;
		endcase
	end
	
	always @ (*)
	begin
		case (state)
			S0: begin
				LA = GREEN;
				LB = RED;
				end
			S1: begin
				LA = YELLOW;
				LB = RED;
				end
			S2: begin
				LA = RED;
				LB = GREEN;
				end
			S3: begin
				LA = RED;
				LB = YELLOW;
				end
			default: begin
				LA = GREEN;
				LB = RED;
				end
		endcase
	end

endmodule

 

// 测试文件：trafficcontrollermoore_test.v
`timescale 1ns / 1ps

module trafficcontrollermoore_test;

	// Inputs
	reg TA;
	reg TB;
	reg clk;
	reg clr;

	// Outputs
	wire [2:0] LA;
	wire [2:0] LB;

	// Instantiate the Unit Under Test (UUT)
	trafficcontrollermoore uut (
		.TA(TA), 
		.TB(TB), 
		.clk(clk), 
		.clr(clr), 
		.LA(LA), 
		.LB(LB)
	);

	initial begin
		// Initialize Inputs
		TA = 0;
		TB = 0;
		clk = 0;
		clr = 0;

		// Wait 100 ns for global reset to finish
		#100;
      
		// Add stimulus here
		clr = 1;
		#100;
		clr = 0;
		#45;
		TA = 1; TB = 0;
		#100;
		TA = 0; TB = 0;
		#200
		TA = 1; TB = 1;
		#100;
		TA = 1; TB = 0;
		#200;
		TA = 0; TB = 1;
		#100;
		clr = 1;
		#100;
		clr = 0;
	end
	
	always # 5
		clk <= ~clk;
      
endmodule

 

// 引脚文件：trafficcontrollermoore_ucf.ucf
NET "clk" LOC = "V10";
NET "clr" LOC = "C9";
NET "TA" LOC = "T5";
NET "TB" LOC = "V8";

NET "LA[2]" LOC = "T11";
NET "LA[1]" LOC = "R11";
NET "LA[0]" LOC = "N11";

NET "LB[2]" LOC = "U15";
NET "LB[1]" LOC = "V16";
NET "LB[0]" LOC = "U16";

 

 

 

15、Traffic controller(Mealy FSM)

Mealy FSM状态转换图

 

// 设计文件：trafficcontrollermealy.v
`timescale 1ns / 1ps

module trafficcontrollermealy(
    input TA,
    input TB,
    input clk,
    input clr,
    output reg [2:0] LA,
    output reg [2:0] LB
    );

	reg [1:0] state, nextstate;
	reg [31:0] count;
	reg mclk;
	
	parameter S0 = 2'b00;
	parameter S1 = 2'b01;
	parameter S2 = 2'b10;
	parameter S3 = 2'b11;
	
	parameter GREEN = 3'b100;
	parameter YELLOW = 3'b010;
	parameter RED = 3'b001;
	
	parameter CLK_COUNT = 249999999; //板级验证的时候该值改为249999999;
	
	always @ (posedge clk or posedge clr)
	begin
		if (clr)
		begin
			count <= 0;
			mclk <= 0;
		end
		else if (count == CLK_COUNT)
		begin
			count <= 0;
			mclk <= ~mclk;
		end
		else
			count <= count+1;
	end
	
	always @ (posedge mclk or posedge clr)
	begin
		if (clr)
			state <= S0;
		else
			state <= nextstate;
	end
	
	always @ (*)
	begin
		case (state)
			S0: if (TA) nextstate = S0;
					else nextstate = S1;
			S1: nextstate = S2;
			S2: if (TB) nextstate = S2;
					else nextstate = S3;
			S3: nextstate = S0;
			default: nextstate = S0;
		endcase
	end
	
	always @ (*)
	begin
		case (nextstate)
			S0: begin
				LA = GREEN;
				LB = RED;
				end
			S1: begin
				LA = YELLOW;
				LB = RED;
				end
			S2: begin
				LA = RED;
				LB = GREEN;
				end
			S3: begin
				LA = RED;
				LB = YELLOW;
				end
			default: begin
				LA = GREEN;
				LB = RED;
				end
		endcase
	end

endmodule

 

// 测试文件：trafficcontrollermealy_test.v
`timescale 1ns / 1ps

module trafficcontrollermealy_test;

	// Inputs
	reg TA;
	reg TB;
	reg clk;
	reg clr;

	// Outputs
	wire [2:0] LA;
	wire [2:0] LB;

	// Instantiate the Unit Under Test (UUT)
	trafficcontrollermealy uut (
		.TA(TA), 
		.TB(TB), 
		.clk(clk), 
		.clr(clr), 
		.LA(LA), 
		.LB(LB)
	);

	initial begin
		// Initialize Inputs
		TA = 0;
		TB = 0;
		clk = 0;
		clr = 0;

		// Wait 100 ns for global reset to finish
		#100;
      
		// Add stimulus here
		clr = 1;
		#100;
		clr = 0;
		#45;
		TA = 1; TB = 0;
		#100;
		TA = 0; TB = 0;
		#200
		TA = 1; TB = 1;
		#100;
		TA = 1; TB = 0;
		#200;
		TA = 0; TB = 1;
		#100;
		clr = 1;
		#100;
		clr = 0;
	end
	
	always # 5
		clk <= ~clk;
      
endmodule

 

// 引脚文件：trafficcontrollermealy_ucf.ucf
NET "clk" LOC = "V10";
NET "clr" LOC = "C9";
NET "TA" LOC = "T5";
NET "TB" LOC = "V8";

NET "LA[2]" LOC = "T11";
NET "LA[1]" LOC = "R11";
NET "LA[0]" LOC = "N11";

NET "LB[2]" LOC = "U15";
NET "LB[1]" LOC = "V16";
NET "LB[0]" LOC = "U16";

 

 

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