芯片间的互连标准: HSIC, UniPro, HSI, C2C, LLI

Updated Interface Standards Table - MIPI HSI, HSIC, UniPro, UniPort, LLI, C2C

芯片间的互连标准: HSIC, UniPro, HSI, C2C, LLI.

There has been a lot of confusion about the different standards for interchip connectivity, with many hardware developers of consumer electronics and mobile computing systems-on-chip wondering what to use. As an interconnect IP provider, I struggle with this every day when working with our customers. I wrote this article to share what I have learned. 

芯片间连接有很多种不同标准，很多消费类产品和移动处理芯片的开发者不知道选用何种标准。做为互连IP提供商，我每天都和我们的客户讨论此问题。我写这个文章来分享我所学到的。

 

Standard
 

Release Date
 

Unidirectional Throughput
 

Pins/Signals/ Channels
 

Low Latency
 

PHY required
 

 

MIPI HSI
 

2003
 

200 Mbit/sec
 

8
 

No
 

MIPI HSI PHY
 

 

USB HSIC
 

2007
 

480 Mbit/sec
 

2
 

No
 

USB 2.0 HSIC PHY
 

 

MIPI UniPro, UniPort-D, and UniPort-M*
 

2007
 

2,900 Mbit/sec per HS-G2 lane5,800 Mbit/sec per HS-G3 lane
 

2 pins per unidirectional lane
 

No
 

MIPI D-PHY or M-PHY
 

 

MIPI LLI*
 

2011
 

2,900 Mbit/sec per HS-G2 lane5,800 Mbit/sec per HS-G3 lane
 

2 pins per unidirectional lane
 

Yes ~80 ns
 

MIPI M-PHY
 

 

C2C
 

2010
 

6,400 Mbit/sec
 

16
 

Yes ~100ns
 

No
 

 

Why interchip connectivity?   为什么要芯片间互连？

The simplest answer is, “Because I want to connect two SoCs together on a PCB with as few traces and as little power consumption as possible.”
 But there are other considerations: 

最简单的答案是：因为想通过少量的连线，并且尽可能低的功耗，在PCB上连接两个芯片。

 但这仍然有其他的问题：

1 Are you connecting your own chips, or chips from other vendors? If from other vendors you will need to research the standards used in those chips. You’ll also need to make sure you match voltages and timings.
     是连接自家的芯片还是芯片来自其他供应商？如果来自其他供应商，你还需要研究这些芯片的标准。你将还需要确定电压和时序的匹配。

2 How many pins do you have available? Some standards like USB HSIC and MIPI LLI only need 2 pins, while others like C2C require at least 24. Application processors are usually more pin-constrained than companion chips or mobile phone modems.
     要用多少个引脚？一些标准，比如：USB HSIC，MIPI LLI只需要两个引脚。而其他的的标准，比如C2C就需要24个引脚。一般来讲，应用处理器都是受协处理器或者手机调制解调器的引脚的限制。

3 How much power can you burn? Only C2C does not require a PHY. USB HSIC still requires a PHY even though it doesn’t require a full transceiver setup like a regular USB connection. MIPI HSI and LLI also require a PHY. Applications processors can usually accommodate another PHY, but companion chips like mobile phone modems or LTE coprocessors may be area or power limited.
     可使用多大的功耗？只有C2C的连接方式不需要物理层。USB HSIC依旧需要使用一个物理层，尽管它不用像普通的USB连接一样需要一个收发设备。

4 Do you want to share memory between the two chips? C2C and MIPI LLI are very low latency interfaces that are fast enough for a mobile phone modem or companion chip to share an application processor’s RAM and to maintain enough read throughput and low latency for cache refills. This enables remote configuration and memory mapped transfers as if the two chips were a single chip. 
     是否需要共享两个芯片的存储器？C2C 和MIPI LLI是低延时的接口，可以足够快的为协处理器或者手机调制解调器分享RAM，并且可以维持足够的读取吞吐率和低延时缓存。这足够使得两个芯片的远程配置和内存映射的传输如同一个芯片一样快。

5 What is the impact on your software ? C2C and LLI are memory-mapped interfaces that only require software intervention to set them up: The actual data transfers do not require any software driver intervention, and one of the chips does not require a driver at all.
     对软件的影响有多大？C2C和LLI是内存映射接口，所以只需要软件去设置它们。真实的数据传输不需要任何软件驱动介入，并且每个芯片根本不需要驱动。

What are the interchip connectivity standards?
 芯片间连接的表示是什么？

USB 2.0 High Speed Inter Chip (HSIC)

HSIC was adopted as a standard by the USB Implementers Forum in 2007. It is a chip-to-chip variant of USB 2.0 that eliminates conventional USB PHYs. The HSIC PHY uses about 50% less power and 75% less area compared to traditional USB 2.0 PHYs. HSIC uses 2 signals at 1.2v and has a throughput of 480Mbit/sec using 240MHz DDR signaling. Maximum PCB trace length for HSIC is 10cm. It does not have low enough latency to support RAM memory sharing between two chips.

HSIC做为一种标准在2007年USB开发者论坛上被采纳。它是芯片到芯片的USB 2.0的变体，并且消除了USB的物理层的惯例。HSIC物理层跟传统USB 2.0的物理层相比，仅使用50%的功耗和25%的面积。HSIC使用2个1.2V的信号，当使用240MHz DDR信号协议时，吞吐率为480Mbit每秒。最大的HSIC布线长度为10cm。它没有足够的低延时，所以不支持内存共享。

MIPI High-speed Synchronous Serial Interface (HSI) v1.0

HSI was created in 2003 and is now managed by the MIPI Alliance. It is the granddaddy of mobile phone inter-chip interconnects and is still present leading SoCs like TI’s OMAP 5 platform. HSI operates at 1.2 or 1.8 volts and has throughout of 200 Mbit/sec. It does not have low enough latency to support RAM memory sharing between two chips.
 HSI标准在2003年被创建，现由MIPI联盟管理。它是祖师级手机芯片内部互连方式，并且现在仍在主导像TI OMAP 5平台的SOC。HSI操作电压在1.2V或1.8V，并且有200Mbit每秒的吞吐率。它没有足够的低延时，所以不支持内存共享。

MIPI UniPro/UniPort v1.4

The UniPro specification was first released in 2007. UniPort is simply UniPro combined with a MIPI D-PHY or M-PHY. A 2-wired differential D-PHY or M-PHY interface supports a maximum data transfer rate of 800 Mbit/sec, but the UniPro data lane is scalable from 1 to 4 lanes for a total throughput of 3.2 Gbit/sec. UniPro is not low latency enough for RAM sharing.
 UniPro规范于2007年第一次发布。uniPort是UniPro和MIPI D-PHY或者M-PHY的简单的组合。两种接法的区别在于，D-PHY 或M-PHY接口支持的最大传输速率为800Mbit每秒，但UniPro的数据通路可以从1到4路扩展以达到3.2Gbit每秒的吞吐率。UniPro没有足够的低延时，所以不支持内存共享。

MIPI Low Latency Interface (LLI)

The MIPI LLI specification will be released in 2011. Its primary purpose is to allow sufficient performance to enable sharing a DRAM memory between 2 chips for data and programs. The main motivation is electronic bill of materials (eBoM) cost reduction. MIPI LLI requires only 2 or 4 pins but does require a MIPI M-PHY capable of Gear 2 for mobile phone use models. Round trip latency is targeted to be 80 nanoseconds using 8 pins in Gear 3, allowing a mobile phone modem or companion chip to share an application processor’s RAM. This saves a minimum of $2 in device eBoM cost, saves PCB space, and reduces device complexity. Unidirectional throughput is 2.9 Gb/sec per lane using MIPI M-PHY Gear 2.

 MIPI LLI规范于2011年发布。它最初的目的是允许足够的性能使的内存共享，已达到Cost Down BOM的作用。MIPI LLI只需要2个或者4个引脚，但必须有MIPI M-PHY Gear 2 用于手机模型。Gear 3中用8个引脚可以使往返延时达到80ns，并允许手机调制解调器或者协处理器共享内存。这样可以节省2美金的BOM成本，节约PCB空间，并且减少设备的复杂性。MIPI M-PHY Gear 2的单向吞吐量为2.9Gb每秒每个通道。

 

C2C Chip-to-Chip

C2C has been available since 2010 and is a product containing technology from Texas Instruments and Arteris. It was created to allow DRAM memory sharing for reduced eBoM cost through a very low latency interface. C2C does not require a PHY, however, unlike MIPI LLI’s 2 or 4 pin requirement, C2C requires about 30  pins total in a mobile phone use model (16 transmit pins, 8 receive pins, plus clock and power pins). The interface can use existing DDR pads and is LPDDR I/O compliant. Round trip latency is 100ns, allowing a modem or companion chip to share an application processor’s memory. At 100,000 gates, C2C is very small. It requires 1.2 or 1.8 volts and has throughput of 6.4 Gb/sec at 200 MHz DDR speeds and using 16 pins.

 C2C从2010年开始被利用，它的技术来自TI和Arteris。它产生的目的是为了实现低延时接口，以内存共享并降低BOM成本。C2C不需要一个PHY，但是，不像MIPI LLI仅需要2个或4个引脚，C2C需要大概总用30个引脚（16个发送引脚，8个接收引脚，另加在加上时钟和电源引脚）。此接口可以使用现存的DDR和LPDDR的I/O标准。往返延时为100ns，以允许调制解调器或协处理器共享内存。在10万门电路里，C2C非常小，它需要1.2V或者1.8V的供电电压，在200MHz DDR的速度下，使用16个引脚， 吞吐量为6.4Gb每秒。

Which interchip connectivity option to choose?
 如何选择芯片互连方案？

The decision on what inter-chip connectivity standard to use is dependent upon a product’s specific use cases and requirements, as well as the interfaces available in the companion products with which it will connect. You will need to understand ahead of time whether you require basic connectivity, or whether you require more exotic features like the memory sharing capabilities delivered by C2C and LLI, and how much embedded software impact this will have on your system.

 Keep in mind that the companion chips with which you would like to connect may have different connectivity requirements and roadmaps than your own products. Therefore it is important to coordinate with the organizations that create these companion chips, whether these teams are in your company or external.

讨论使用何种芯片互连标准，主要取决于产品使用情况和需求，而且你的相关产品是否有此接口。你首先需要知道，你是需要简单的互连，或者你需要更多的比如像C2C和LLI 共享内存的能力？另外你还要评估对你系统的嵌入式软件的影响。

需要注意的是，你需要了解选择的协处理器可能和你自己的产品有不同的连接需求和产品规划。所以无论协处理芯片是你公司的还是外部公司的，协调组织非常重要

本文来自：我爱研发网(52RD.com) - R&D大本营
详细出处：http://www.52rd.com/Blog/Archive_Thread.asp?SID=66736